SoC Endpoint Resets

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

There are three SoC endpoint system-level resets (SYS_RST) routed to the NPI register modules in the SoC where one or more of these resets can be enabled (unmasked) to reset the associated block. The SYS_RST reset signals are controlled by three bits in the CRP. RST_NONPS register as shown in the following table. Each NPI-based PCSR register set includes a register with three mask bits for the three SYS_RST reset signals from the PMC reset controller.

Note: These resets do not have an effect on the CRP.RESET_REASON register.
Table 1. SoC Endpoint Reset Register Controls
Reset Signal Name CRP. RST_NONPS Bit Name Description

SYS_RST_1

[SYS_RST_1]

System reset 1 bused to NPI register modules

SYS_RST_2

[SYS_RST_2]

System reset 2 bused to NPI register modules

SYS_RST_3

[SYS_RST_3]

System reset 2 bused to NPI register modules