The four AXI interfaces to NoC can be individually mapped to system memory or striped to improved throughput. Striping can be across two (in pairs) or all four of the AXI interfaces to NoC.
Almost all of the memory ranges for the CCI can be striped AXI are striped. The default stripe size is 4 KB. This means accesses to the striped memory regions come out on one of the four CCI outgoing ports AXI 2, AXI 3, AXI4, and AXI 5. However, the memory range between 2 TB and 4 TB is not striped. Accesses to the region from 0x200_0000_0000 to 0x3FF_FFFF_FFFF always come out on a single port. This memory range maps to the PL NoC address space. The assigned port depends on the CCI configuration defined in three LPD_SLCR registers listed in the CCI Register Reference section.
- If an incoming port is configured for 4-way interleaving, or
2-way on outgoing ports AXI 2 and AXI 3, then:
- Traffic in the 2 TB to 3 TB memory space range is routed to CCI port AXI 2
- Traffic in the 3 TB to 4 TB memory space range is routed to CCI port AXI 3
- If an incoming port is configured for 2-way interleaving on
outgoing ports AXI 4 and AXI 5, then:
- Traffic in the 2 TB to 3 TB memory space range is routed to CCI port AXI 4
- Traffic in the 3 TB to 4 TB memory space range is routed to CCI port AXI 5
- The 290 GB reserved address space above the PL-via NoC region (see reserved address space) is still routed to the NOC (DDR region). It is expected that the NoC will issue a decode error for this reserved space to reduce the timing impact in the CCI address decoder.
The first configuration (1) is the default setting. All of the ePorts are configured for 4-way striping so the address range 0x200_0000_0000 to 0x2FF_FFFF_FFFF is routed to the CCI port AXI 2 while 0x300_0000_0000 to 0x3FF_FFFF_FFFF is routed to the CCI port AXI 3.