Subsystem Resets

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The subsystem resets are shown in the following table.

Table 1. Subsystem Resets
Description Reset Name Power Domain Register Bit Control
CRP RST_DBG register
All CoreSight components inside of the PMC and PS     [RESET]
Debug port controller DPC_RESET PMC [DPC]
CRL RST_CPU_R5 register
RPU MPCore, and debug logic RPU_POR_RESET LPD [RESET_POR_RPU]
TCMs, GIC, and 2x1 switch RPU_AMBA_RESET LPD [RESET_AMBA]
RPU CPUs

RPU_CPU0_RESET
RPU_CPU1_RESET

LPD

[RESET_RPU1]
[RESET_RPU0]