System Features

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The PS is described in the Processing System section.

The PMC is described in the Platform Management Controller section.

NoC Interconnect

The NoC interconnect is pervasive across the device. See Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313).

DDR Memory

The device includes one or more DDR4/LPDDR4 memory controllers.

HBM Memory

Some devices include one or more high-bandwidth memory interfaces that attach to the NoC interconnect and drive I/O buffers to the HBM die within the device. See High-Bandwidth Memory Interface.

Programmable Logic

The PL is a scalable structure that provides the ability to create many possible functions. The integrated hardware options have interconnect interfaces and connections to the PL fabric. The PL I/O includes both LVCMOS buffers and gigabit transceivers that cover a wide range of applications and frequencies. See PL Fabric Overview.

Integrated Hardware Options

Coherent Module with PCIe

The coherent module with PCIe (CPM) interconnect provides coherency between the PCIe controllers, a PL processor, and the PS. The CXL module adds memory coherency with external devices over PCIe.

See Integrated Hardware Options. There are multiple types of CPM modules:

  • CPM4 with CCIX interconnect (device option in Versal ACAP)
  • CPM5 with CXL interconnect (device option in Versal ACAP)