The registers in this section are associated with the system. This includes the DMA AXI interface and various clock and reset signals. All registers are 32 bits wide.
Note: The interrupts are included in the Interrupt and Status Registers section.
| Register Name | Access Type | Description | |
|---|---|---|---|
| SD_eMMC 0 | SD_eMMC 1 | ||
| Reference Clock Controls in the CRP register module | |||
| SD0_REF_CTRL | SD1_REF_CTRL | RW | SD_eMMC reference clock for DIV_CLK module. |
| SDIO_DLL_REF_CTRL | RW | Program DLL reference clock frequency for both SD DLL modules. Write protected. | |
| RST_SDIO0 | RST_SDIO1 | RW | Controller is also reset when the PMC is reset. Device-level resets are included in the Resets Overview section. |
|
|
RW | I/O interface routing through the MIO multiplexer and pins, see Multiplexed I/O Signals and Pins. | |
| DMA Transaction Controls for Interconnect in the PMC_IOP_SLCR register module | |||
| RW | AXI transactions: coherency, route to the memory coherent interconnect, and QoS. | ||