System Watchdog Timers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The system watchdog timer (SWDT) includes a multifunctional window operating mode and a generic timeout mode. In window mode, the system software must write to the watchdog timer within predefined window periods of time. In the simplest case, this means a period that is not too soon and a period that is not too late. The basic window mode includes an option that requires the software to perform a task signature handshake with the watchdog timer. The Q&A window mode includes a token protocol that requires software to calculate response values and write byte values four times during certain times. The window mode also includes an optional second sequence timer to delay an inevitable system reset request event.

Watchdog timers are commonly used in embedded systems to activate fail-safe circuitry in the event of a fault. The programmable watchdog timer helps to maintain a healthy and secure system by detecting errant software, deadlock conditions, tampering, and unexpected behavior. The window mode timer does this by imposing strict requirements on the software. If there is unexpected software behavior, there is a greater probability that software cannot fulfill the strict response requirements of the timer, which can cause a bad event that either adds to the fail counter or leads to the system reset request event.

The system reset event is signaled as a system error for the PSM firmware to handle and a reset output signal to the MIO/EMIO.

There are two instances of the SWDT; one in the LPD and one in the FPD.