System-level Clock and Reset Registers

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The clock and reset control registers are summarized in the following table.

Table 1. I2C Clock and Reset Registers
Register Name Address Access Type Description Signal Name
PMC_I2C
I2C_REF_CTRL 0xF126_0130 RW Reference clock PMC_I2C_REF_CLK
RST_I2C 0xF126_0314 RW Controller reset PMC_I2C_RESET
LPD_I2C0
I2C0_REF_CTRL 0xFF5E_0140 RW Reference clock LPD_I2C0_REF_CLK
RST_LPD_I2C0 0xFF5E_0330 RW Controller reset LPD_I2C0_RESET
LPD_I2C1
I2C1_REF_CTRL 0xFF5E_0144 RW Reference clock LPD_I2C1_REF_CLK
RST_LPD_I2C1 0xFF5E_0334 RW Controller reset LPD_I2C1_RESET