TAP Controller Instruction Availability

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The JTAG dedicated I/O supports boundary-scan operations, status register access, boot operation, and a single-stepping hardware analyzer in the PL and AI Engine. The JTAG interface provides base debug to assist with board or device bring-up issue isolation.

The TAP controller instructions are listed in the JTAG TAP Instructions section. The availability of an instruction depends on the state of the device as shown in the figure in this section.

If JTAG is disabled, via the JTAG disable eFUSE, only the IDCODE JTAG instruction is available. This is a permanent setting and cannot be reverted. See the Versal Adaptive SoC Security Manual (UG1508) for the production readiness of the desired security feature, as well as its detailed usage instructions. This manual can be downloaded from the Design Security Lounge.
Important: An active NDA is required for access to the Design Security Lounge.

If the JTAG disable eFUSE is not set, on power-up, the default boot mode is secure and the JTAG interface accepts the base JTAG instructions regardless of the boot mode. For non-secure boot, after the boot is complete, successfully or unsuccessfully, the full suite of extended JTAG instructions are enabled. For secure boot, if the boot is completed successfully, the authenticated software is capable of enabling the extended JTAG instructions. In the event of a failed secure boot, the JTAG capabilities are dependent on how the device was provisioned.

The following figure illustrates the JTAG interface protections, as well as when the base JTAG instructions or full extended instructions are available.

Figure 1. JTAG Instruction Access