The JTAG dedicated I/O supports boundary-scan operations, status register access, PL readback, and a single-stepping hardware analyzer in the PL and AI Engine. The JTAG interface provides base debug to assist with board or device bring-up issue isolation.
The TAP controller instructions are listed in the JTAG TAP Instructions section. The availability of an instruction depends on the state of the device as shown in the figure below.
If the JTAG disable eFUSE is not set, on power-up, the default boot mode is secure and the JTAG interface accepts the base JTAG instructions regardless of the boot mode. For non-secure boot, after the boot is complete, successfully or unsuccessfully, the full suite of extended JTAG instructions are enabled. For secure boot, if the boot is completed successfully, the authenticated software is capable of enabling the extended JTAG instructions. In the event of a failed secure boot, the JTAG capabilities are dependent on how the device was provisioned.
The following figure illustrates the JTAG interface protections, as well as when the base JTAG instructions or full extended instructions are available.