The low-latency, tightly-coupled memories (TCMs) provide predictable instruction execution and predictable data load/store timing for the RPU processors. TCM memory address space is not cached.
Each RPU processor contains two 32 KB memories and one 64 KB memory that are accessed via the TCM A and B port interfaces, for a total of 128 KB per processor. In lock-step mode, the processor has access to 256 KB of TCM memory.
The parallel memory architecture of the RPUs allows concurrent accesses of all three banks by the CPU's load-store unit, instruction prefetch unit, and AXI destination port. The TCM_B includes two 32 KB banks for concurrent, parallel access.
Datapaths are 64-bits wide and are protected by ECC. Each CPU includes three datapaths to:
- 64 KB in TCM_A
- 32 KB in TCM_B0
- 32 KB in TCM_B1
TCMs are accessible after the processor is taken out of reset. The processor must be inactive (idle) or in the halt state to allow another processor to access the TCMs. The processors have direct connections to their TCMs for low-latency access and there are no protection units.
The datapaths through the RPU are shown in Processor Memory Datapaths.
The TCMs can be used for any purpose, but are typically used as follows:
- TCM_A for interrupt or exception code for high speed, without cache miss delays
- TCM_B for data in process-intensive applications such as audio or video processing
The PSM controls power islands for each 64 KB TCM bank using register controls. The power islands are described in Power Islands. All TCMs should be powered up or down together.