Timer Signals to System, MIO, and EMIO

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The IRQ numbers for the watchdog timers are listed with all other system interrupts in IRQ System Interrupts.

Note: All of these signals are outputs from the watchdog timer. The system interrupts are level sensitive, active-High.
Table 1. SWDT Signals to the System, MIO, and EMIO Descriptions
Description Window Basic Mode Window Q&A Mode Generic Mode System Signal MIO Signal Name EMIO Signal Name
Name IRQ

Main interrupt

Active-High interrupt output asserted when an interrupt bit in the Enable_and_Status register is set and not masked. Enable and status for the interrupts G_CSR .

LPD_SWDT_INT
FPD_SWDT_INT

81
132

Active-High:
SWDT0_INT
SWDT1_INT

FMIOWWDTINTERRUPT
FMIOFPDWWDTINTERRUPT

Applicable bits: [WINT], [WRP] [GWEN], [GWS]
Reset to I/O signal to MIO/EMIO Asserted after a bad event (or when the fail counter overflows, if enabled). The controller auto disables itself (clears the [WEN] bit) and waits to receive a reset. Asserts on second expiration of the timeout counter. - N/A

Active-High:
SWDT0_RST
SWDT1_RST

FMIOWDTRESET
FMIOFPDWWDTRESET

Error signal assertion for PSM

PSM_GLOBAL.PSM_ERR2_STATUS
[LPD_SWDT], [FPD_SWDT] bits

PSMERRORTOPL[32]
PSMERRORTOPL[33]

Pending interrupt Asserted after a bad event. The controller auto disables itself (clears the [WEN] bit) and waits to receive a reset. Asserts on the second window timeout.

Level Interrupt:
LPD_SWDT_INT_PEND
FPD_SWDT_INT_PEND

101
141

Active-High:
SWDT0_RST_PEND
SWDT1_RST_PEND

FMIOWWDTRESETPENDING
FMIOFPDWWDTRESETPENDING

Generic window 0 indicator N/A Generic timer window 0 active.

LPD_SWDT_INT_GWS0
FPD_SWDT_INT_GWS0

102
140

Active-High:
SWDT0_GWS0
SWDT1_GWS0

FMIOGWDTWS0
FMIOFPDGWDTWS0

Generic window 1 indicator N/A Generic timer window 1 active.

LPD_SWDT_INT_GWS1 FPD_SWDT_INT_GWS1

103
142

Active-High: SWDT0_GWS1 SWDT1_GWS1 FMIOWDTWS1 FMIOFPDGWDTWS1