The timestamp unit (TSU) clock signal can be sourced from the LPD clock controller, an MIO pin, or a EMIO port interface signal. The TSU clock is programmed using the registers listed in System-Level Registers. There is one clock shared by both GEM controllers.
|Signal Name||I/O||PMC MIO Pin||LPD MIO Pin||MIO-at-a-Glance Table||Signal Name||I/O|
The CTRL signals control the incrementing of the timer. The timer increments:
- 00: based on the gem_tsu_ms value
- 01: by an additional nanosecond
- 10: by one nanosecond fewer
- 11: normally