Transaction Checking Operations

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

For every read and write transaction, the XPPU determines if the transaction is allowed to proceed with fine grain control of specific addresses. If the transaction is allowed, then it proceeds normally. If the transaction is not allowed, it asserts an error flag that is detected downstream.

An AXI transaction request is allowed to access the address space defined by an APERPERM_xxx register (example APERPERM_000 ) if these conditions are satisfied:

  • The AXI transaction SMID fits one (or more) of the profiles defined in the SMID_xx registers
  • The AXI address selects an aperture that enables the selected SMID_xx register and its [permission] bit field
  • The transaction request satisfies the [TRUSTZONE] register bit setting