Processors and peripherals with DMA units generate transactions on the interconnect. The attributes associated with each transaction comes from the host that initiated the transaction and logic that might add or alter the signals originating from the host. This can include adding an address offset to a 32-bit processor, make cache-coherent, and add a QoS value. The transaction attributes guide the request through the interconnect to its destination.
Transactions from the LPD hosts can be individually routed directly to memory or to the FPD SMMU TBUs and the memory coherent interconnect for shared memory and coherent transactions.
Execute-in-Place not Supported
All processors execute instructions from their local caches and memory. The interconnect does not support execution-in-place (XIP).