Transaction Routes

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

Transactions are mainly routed by their address. However, there are transactions from the PL, LPD, and CPM that can be routed directly to memory or to the system memory management unit (SMMU) and the cache coherent interconnect (CCI) in the FPD using register controls. The route through the SMMU uses a 48-bit virtual address that is translated to a 44-bit physical address. This translation enables a shared memory environment with other processors. This route requires the cache signals to be valid because the CCI must decide how to handle the transaction I/O coherency with the APU L2 and PL system caches. Coherency checking can be disabled by declaring the transaction as non-cacheable in AxCACHE. In this case, the transaction flows through the CCI without disturbing the caching system.

The routing and coherency options are listed in the Routing and Coherency Controls section.

Cache transaction are identified using the four AxCACHE bits. The encoding is shown in the AxCACHE section. In some cases, the host generates these four bits on a per transaction basis. In other cases, the AxCACHE bits are defined by register settings. In this situation, a register write is required to switch a host between coherent and non-coherent transactions.