The AXI memory transactions have several attributes controlled by the LPD_IOP_SLCR register set. The transactions can be coherent to the system cache in the FPD by routing the transaction to the coherent interconnect via the SMMU. The AXI coherency signals are programmed to request the caching policy. This programming is used for both reads and writes:
- GEM0_Route [GEMx] routes the transactions through the FPD coherent interconnect to the system cache.
- GEM0_Coherent [GEMx_AXI_COH] defines the AxUSER signals for the caching policy used by the coherent interconnect AXI-Lite connection.
The encoding of [GEMx_AXI_COH] bit field controls DMA AXI transaction coherency with respect to the system cache and transaction buffers on the interconnect.
When the transaction bypasses the CCI, the [GEMx_AXI_COH] is only used to define the bufferability of the transaction. The coherency settings are ignored.