The AXI memory transactions have several attributes controlled by the LPD_IOP_SLCR register set. The transactions can be coherent to the APU L2-cache by routing the transaction to the CCI via the SMMU. The AXI coherency signals are programmed to request the caching policy. This programming is used for both reads and writes:
- GEM0_Route [GEMx] routes the transactions through the CCI, which is required for coherency to the APU L2-cache.
- GEM0_Coherent [GEMx_AXI_COH] defines the AxUSER signals for the caching policy used by the CCI AXI-Lite connection.
The encoding of [GEMx_AXI_COH] bit field controls DMA AXI transaction coherency with respect to the APU L2-Cache and transaction buffers on the interconnect.
When the transaction bypasses the CCI, the [GEMx_AXI_COH] is only used to define the bufferability of the transaction. The coherency settings are ignored.