The protection units compare the credentials of the transaction with the access controls for each address location. The MMUs restrict access using page table faults.
- XMPU protection units
- XPPU protection units
- APU MPCore MMU page mapping
- FPD SMMU page mapping
The following table summarizes the types of protection units.
| Access Unit | Description |
|---|---|
| APU MPCore MMU | Monitors the transactions from the APU processors. |
| FPD SMMU | The SMMU includes one translation control unit (TCU) and six translation buffer units (TBU). The SMMU provides protection (and address translation) for all non-APU transactions targeting the PS address space. The protection functionality is applied to the physical address that occurs after the address translations. The SMMU registers are accessible only from the APU. |
| XMPU | The AMD memory protection units (XMPU) provide address partitioning and TrustZone protection for memories; the XMPU instances are listed in the Xilinx Memory Protection Unit section. |
| XPPU | The AMD peripheral protection units (XPPU) provide address partitioning and TrustZone protection for access to peripherals. The XPPU instances are listed in the Xilinx Peripheral Protection Unit section. |
| Secure registers | There are several register programming interfaces that always require a secure transaction, which is often in addition to passing through another security unit. These are listed in Always-Secure Register Programming Interfaces. |