Versal ACAP Technical Reference Manual (AM011)

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1.4 English

Several of the UltraRAM key features are listed in this section. For additional features and functionality, see the Versal ACAP Memory Resources Architecture Manual (AM007).


  • 32 KB of data storage, 4K x 9 bytes (64-bit data plus 8-bit ECC)
  • Dual port, single-clock synchronous memory
  • Cascade-able for building larger memories, dedicated column routing wires to connect adjacent UltraRAM units
  • ECC on both ports with single bit error detection and correction, and double bit error detection
  • Sleep power saving features
Synchronous Operation Only
Each memory access, read, and write is controlled by the clock. All inputs, data, address, clock enable, and write enable are registered. The data output is always latched, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.
Asynchronous Operation
The data outputs can also be set or reset asynchronously. Sleep input (places the memory array in low-power state) can be optionally asynchronous.
Pseudo Dual-port Operation
There are two ports on the memory. Each port is capable of reading or writing in a single cycle. The ports are sequenced in a fixed order, allowing up to two transactions per cycle (both ports write, both ports read, or one port reads while the other writes.) This necessitates that the two ports share a common clock. During a write operation, the data output remains unchanged on a given port. There is independent reset control of output latches and registers.

The error-correction code (ECC) logic in the UltraRAM supports real time error checking and correction. Both ports have dedicated ECC for either read or write. The ECC logic is organized for 64-bit-wide data, which can generate, store, and use eight additional bits to perform single-bit error correction and double-bit error detection during the read process.

It is possible to cascade the address and data of adjacent blocks to build deeper memories. Optional pipelining is also available to maintain the clock rate through tall cascades of UltraRAM.

Comparison to Previous Generation Xilinx Devices

The Versal device UltraRAM is very similar to the UltraRAM in the UltraScale+™ device. There are multiple UltraRAM columns distributed in the PL. Improvements include asymmetric port widths, memory initialization values, and data cascade ordering.