The Versal ACAP new PMC centralized integration provides support for basic boot and configuration, Dynamic Function eXchange (DFX), power management, and reliability and safety functions from a single controller. The PMC bus architecture enables significantly faster configuration and readback performance when compared with previous architectures. The following table summarizes the boot mode differences between architectures.
| Mode | Virtex UltraScale+ or Kintex UltraScale+ FPGA | Zynq UltraScale+ MPSoC or Zynq UltraScale+ RFSoC | Versal ACAP |
|---|---|---|---|
| JTAG | Yes | Yes | Yes |
| OSPI | – | – | Yes |
| QSPI32 |
Yes |
Yes |
Yes |
| QSPI24 |
Yes |
Yes |
Yes |
| SelectMAP | Yes | – | Yes 1 |
| eMMC1 (4.51) | – | Yes | Yes |
| SD1 (3.0) | – | Yes | Yes |
| SD1 (2.0) | – | Yes | Yes |
| SD0 (3.0) | – | – | Yes |
| SD0 (2.0) | – | Yes | – |
| PJTAG_0 | – | – | – |
| PJTAG_1 | – | Yes | – |
| Serial | Yes | – | – |
| BPI | Yes | – | Note 2 |
| NAND | – | Yes | Note 2 |
| USB (2.0) | – | Yes | – |
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Additional key differences from previous generations are:
- PMC has its own dedicated power domain. Unlike the Zynq UltraScale+ MPSoCPS CSU and PMU, the Versal ACAP PMC, RCU, and PPU are decoupled from the PS or PL power domains.
- Configuration frame interface (CFI) bus is dedicated to accessing the configuration frames and provides configuration and readback performance improvements. In conjunction with the network on chip (NoC), it replaces the internal configuration access ports (ICAP, PCAP, and MCAP) used in previous generations.
- NoC programming interface (NPI) provides register access for remote peripherals such as gigabit transceivers and DDR memory.
- Octal SPI boot mode supports compatible octal SPI flash memory with DDR mode providing a high-speed and low pin-count solution.
- SelectMAP boot mode loads configuration data and requires hardware flow control using a BUSY signal.
- Single TAP located in the platform management controller.
- Single DNA identification accessible via JTAG or in the AXI register set. Versal ACAP does not have a PL DNA or a corresponding PL DNA_PORT primitive.
- Internal configuration clock provides higher performance than prior generation.
- Debug packet controller (DPC) supports the high-speed debug port (HSDP) for processing packets from interfaces including HSDP Aurora and PCIe controllers.
- Integrated system monitor in the platform management controller.
- Enhanced encryption and decryption for increased resistance to differential power attacks (DPA).
- Two PUF outputs that are exclusively managed by the RCU, a unique readable device ID, and a unique device key encryption key (KEK) for encrypt/decrypt.
- Enhanced authenticated JTAG (RSA/ECDSA) access via JTAG.
- True random number generator (TRNG), additional AES user keys, and ECDSA authentication added for security applications.
- Connections from the gigabit transceivers, through the CPM and through LPD into the PMC configuration.
- The legacy quad SPI (LQSPI) controller mode is not supported in the Versal ACAP.
- Execute-in-place (XIP) is not supported by Versal device boot modes.
- JTAG accessible internal private scan registers (with USER1-4 commands) are accessed with the PS9 primitive through the control, interface, and processing system (CIPS) IP. The Versal ACAP does not have a BSCANE2 primitive.
- The Xilinx soft error mitigation (XilSEM) library is a pre-configured and pre-verified solution to detect and optionally correct soft errors in the configuration memory of Versal ACAPs.