Versal ACAP Technical Reference Manual Outline

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The Versal ACAP Technical Reference Manual describes the overall hardware architecture of the Versal ACAP and the technical details of both the processing system (PS) and the platform management controller (PMC). The documentation for NoC, DDR, and optional integrated hardware is included in the

The control and status registers for the PS and PMC are described in the Versal ACAP Register Reference (AM012). For security-minded applications, see the Versal ACAP Security Register Reference Manual (AM018), which requires an active NDA to download from the Design Security Lounge.

The TRM is divided into sections that provide hardware architecture information on the PS and the PMC. The TRM also provides references to companion documentation that complement the TRM and provide detailed information outside of the PS and the PMC.

The outline of the TRM is described in this section.

Device and Document Overview

Introduction provides an introduction to the SoC devices.

The TRM technical content begins with Hardware Architecture. This is a hardware-centric section that covers the entire device. This section includes links to other parts of the TRM and to companion documents that include extensive technical information.

Platform Boot, Control and Status Functionality

The reset response, boot flow, and runtime services are provided by the PMC. The start-up activities of the PMC are described in Platform Boot, Control, and Status. The chapters in this section describe how the device comes up after a reset and how to manage the platform during normal device operation.

Global Address Maps and Signals

The TRM includes two reference sections for address maps, control register summaries, and tables that list the signals, interfaces, and pins. These sections include device-wide content.

PMC and PS Hardware

The remainder of the TRM includes multiple technical reference sections that illustrate the detailed architectures and describe the functional models of each block in the PMC and PS.

Clocks, Resets, Power, Test, and Debug

The clocks, resets, power, test, and debug are described in the following sections.