The features and options along with the window mode activity is shown in the following table.
|Features and Options
|Basic Window Mode
|Q&A Window Mode
|Closed window time period
|See Window Watchdog Timer Mode
|Open window time period
|Second window, reset request event pending, and wrong configuration
|Status in the Enable_and_Status register
|Second sequence timer (SST)
|Delay with pending reset followed by reset
|Option, Basic Program Sequence Monitor
|Program sequence monitor (PSM)
|Simple handshake with software
|Option, Basic Program Sequence Monitor section
|Q&A token exchange
|Complex handshake with software
|See Q&A Token Response Bits Table section
|Fail counter events
Second Window Interrupt
The timing for the second window interrupt is described in the following figure.
Second Sequence Timer
The second sequence timer (SST) is an additional timer that can be used to delay the inevitable watchdog timer reset. This delay can be useful in applications where software needs to log the data for debug work.
The SST can be enabled in basic and Q&A window modes.
When the second sequence timer is enabled, the SWDT_INT_PEND system interrupt signal and the SWDT_RST_PEND output signal to the MIO/EMIO remain asserted until the watchdog timer is reset.
The 3-bit fail counter (FC) keeps track of the accuracy of the interactions between the software and the watchdog timer. The fail counter tracks good and bad watchdog events. For every good event, the fail counter decrements by 1 (unless it is at 0). For every bad event, the fail counter increments by 1 (unless it is at 7).
When the FC is 7 and another bad event occurs in the first window, the timer continues counting through the first window but skips the second window. If the SST window is enabled, the pending reset event occurs followed by the eventual system reset.
When the FC is 7 and another bad event happens in the second window, the timer immediately goes to either the SST window (if enabled) or directly to asserting the system reset.
The watchdog timer can only be disabled when the fail counter is 0.
The FC reset value is 5 but can be changed by software before enabling the watchdog timer.
- FC in basic mode (optional)
- The fail counter is enable by the Funct_Ctrl [FCE] bit
- FC in Q&A mode
- Always enabled