XHCI Registers

Versal Adaptive SoC Technical Reference Manual (AM011)

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The USB_XHCI registers provide functionality for the xHCI specification. The base address for these registers is 0xFE20_0000 and they are summarized in the following table.

Table 1. USB_XHCI Register Address Map
Description Offset Address Range Detailed Register Table
Start End
xHCI capabilities, offsets, operations 0x0_0000 0x0_0058  
Ports, runtime, host interrupter, event ring, doorbells 0x0_0420 0x0_05E0  
Miscellaneous control, status, capabilities 0x0_08E0 0x0_09C0  
Miscellaneous configuration, control, and user 0x0_C100 0x0_C19C  
ULPI PHY 0x0_C200 0x0_C280  
FIFOs 0x0_C300 0x0_C388  
Event buffer 0x0_C400 0x0_C43C  
DMA 0x0_C600 0x0_C630  
Device CSRs 0x0_C700 0x0_C720  
Device endpoints 0x0_C800 0x0_C8BC  
Device interrupt moderation 0x0_CA00 0x0_CA0C