XMPU Register Set

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID: AM011
Release Date: 2023-10-05
Revision: 1.6 English

The XMPU registers are listed in the following table and described in the XMPU register module.

Table 1. Adaptive SoC XMPU Register Overview
Register Name	Offset Address	Access Type	Register Count	Description
XMPU Control and Status
CTRL	`0x0000`	RW, R	1	Default read/write and alignment configuration
ERR_STATUS1_LO ERR_STATUS1_HI ERR_STATUS2	`0x0004`+	R	3	SMID value (FPD_XMPU)
ISR IMR IER IDR	`0x0010`+	WTC R W W	4	Interrupt controls: address decode error, transaction violations
LOCK	`0x0020`	RWSO	1	Restricts writes, see XMPU Write Lock section
XMPU Regional Controls
R00_START_LO R00_START_HI (00 to 15 registers)	`0x0100`+	RW	32	Region starting base address
R00_END_LO R00_END_HI (00 to 15 registers)	`0x0104`+	RW	32	Region ending base address
R00_SMID (00 to 15 registers)	`0x0108`+	RW	16	Region SMIDs
R00_CONFIG (00 to 15 registers)	`0x010C`+	RW	16	Region profile: enable, read/write allowed, secure level, relaxed checking