XPPU Implementations

Versal Adaptive SoC Technical Reference Manual (AM011)

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1.6 English

The AMD peripheral protection unit (XPPU) in the Versal adaptive SoC is similar to the one in the Zynq UltraScale+ MPSoC except in the way an error is handled. The default setting is to deny a transaction.

Table 1. XPPU Peripheral Protection Unit Implementations
Device Generation Isolation, Parity, Protection, and Integrity Checking Error Handling Total Number of Apertures Dynamic Reconfiguration
UltraScale+ MPSoC Inserted on AXI channels Poison the base address

128x 32 B (IPI msg buffer)
256x 64 KB
16x 1 MB
1x 512 MB

Versal device Embedded into interconnect switches Issue a fail message on the interconnect back to initiator

256x 64 KB
16x 1 MB
1x 512 MB