XPPU Register Set

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English
The XPPU registers are listed in the following table. The base address for each XPPU is included in the XPPU Instances table.
Table 1. XPPU Register Summary
Register Name Offset Address Access Type Register Count Description
Control and Status
CTRL 0x0000 RW 1 Default read/write and alignment configuration

ERR_STATUS1
ERR_STATUS2

0x0008, 0x000C

R

2 Address and SMID of violation transaction

ISR,
IMR
IEN,
IDS
ITR

0x0010
0x0014
0x0018
0x001C
0x000C

WTC
R
W
W
R

5

Interrupt controls: address decode error, transaction violations.
Status
Mask
Enable
Disable
Trigger

LOCK 0x0020 RWSO 1 Write a 1 to lock register writes. To unlock, a POR reset is required, a subsequent write of 0 is ignored.
Aperture Address Size

APERTURE_64KB
APERTURE_1MB
APERTURE_512MB


0x0044
0x0048
0x004C

R

3



Number of SMID registers
SMID_REG_COUNT 0x0040

R

1 Software can define 20 incoming AXI transaction profiles. Read-only.
Base Addresses


            BASE_64KB
        


            BASE_1MB
        


            BASE_512MB
        


0x0054
0x0058
0x005C

R 3

The address of these apertures are different for the LPD, PMC and PMC_NPI units. The addresses are defined in the register manual.

System Management ID

SMID_nn
(20 registers)

0x0100 to 0x014C RW 20 Each register defines a set of acceptable SMID values via masks and a read/write settings
Aperture Registers
APERPERM 000 to 255 0x1000 to 0x13FC RW 256 64 KB page
Reserved 0x1400 to 0x15FC - - -
APERPERM 384 to 399 0x1600 to 0x163C RW 16 1 MB page
APERPERM 400 0x1640 RW 1 512 MB page dedicated to the OSPI memory linear addressable space