eMMC1 Register Boot Settings

Versal ACAP Technical Reference Manual (AM011)

Document ID
AM011
Release Date
2022-04-26
Revision
1.4 English

The BootROM sets configuration registers that apply to each boot mode. For eMMC1 boot mode, the BootROM sets the registers to the initial values shown in the following table.

Table 1. eMMC1 Register Boot Settings
Register Name Base Address Register Value Description
SD1_REF_CTRL 0xF126_0128 0x0100_1200 Select PPLL divided by 18 (DIVISOR), clock enabled
SD1_Clk_Ctrl 0xF106_0480 0x0000_0000 eMMC1 I/O feedback clock control MIO[0] selected
MIO_Bank0_Schmitt_En 0xF106_010C 0x0000_1FF9 Enable Schmitt on eMMC1 MIO pins
MIO_Bank0_Tristate 0xF106_0200 0x03FF_E006 Disable 3-state override on eMMC1 MIO pins
RST_SDIO1 0xF126_030C 0x0000_0000 SDIO RST not asserted
SD1_Cfg_Reg1 0xF106_0490 0x0000_1E50 Base clock frequency, sync wake-up mode
SD1_CD_Ctrl 0xF106_04CC 0x0000_0000 CD signal from SD/eMMC is used
SD1_Ctrl 0xF106_0484 0x0000_0001 eMMC1 enabled
SD1_Cfg_Reg2 0xF106_0494 0x0000_1FFC eMMC1 configuration setup
PMCPLL_CTRL 0xF126_0040 0x0002_4800 PMC PLL (PPLL) setup uses reset defaults (REF_CLK multiplied by 72 (FBDIV) and divided by 4 (CLKOUTDIV)