In eMMC1 boot mode, the MIO[0, 3:12] are configured by the BootROM to use:
- Default drive strength (8 mA)
- Default slew rate (slow)
- Default weak pull-ups (enabled)
- Enables the Schmitt trigger
- Disables the 3-state override
The remaining MIOs are not set by the BootROM and remain at their default state. If a secure lockdown occurs during boot, the BootROM sets the PMC_GLOBAL TRISTATE_OVERRIDE register to force all I/Os into a tristate mode. This register is then reserved for use by the PLM firmware.
The following table lists the bidirectional PMC multiplexed I/Os (MIOs) and their functions used in the eMMC1 boot mode setup.
| PMC MIO Pin | Signal Name | Description |
|---|---|---|
| 0 | EMMC1_CLK | eMMC1 clock output |
| 3 | EMMC1_CMD | eMMC1 command |
| 4 | EMMC1_DATA[0] | Data pin used in eMMC1 boot mode (1-bit, 4-bit, 8-bit) |
| 5 | EMMC1_DATA[1] | Data pin used in eMMC1 boot mode (4-bit, 8-bit) |
| 6 | EMMC1_DATA[2] | Data pin used in eMMC1 boot mode (4-bit, 8-bit) |
| 7 | EMMC1_DATA[3] | Data pin used in eMMC1 boot mode (4-bit, 8-bit) |
| 8 | EMMC1_DATA[4] | Data pin used in eMMC1 boot mode (8-bit) |
| 9 | EMMC1_DATA[5] | Data pin used in eMMC1 boot mode (8-bit) |
| 10 | EMMC1_DATA[6] | Data pin used in eMMC1 boot mode (8-bit) |
| 11 | EMMC1_DATA[7] | Data pin used in eMMC1 boot mode (8-bit) |
| 12 | EMMC1_RST | Reset output that resets the eMMC flash |