ePort Timeout

Versal ACAP Technical Reference Manual (AM011)

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1.5 English

The ePort timeout unit monitors the amount of time that a transaction is waiting on the attached block (programming interface or data port). If the amount of time exceeds a threshold, the timeout unit provides an AXI bus error response back to the initiator and raises an error flag. A timeout condition can be caused by several situations, such as an unresponsive or misbehaving block that is:

  • Powered-down
  • In its reset state
  • Congested
  • Deadlocked

Once the ePort has timed out, it responds to all pending and subsequent requests with an AXI bus error response. The user should treat all endpoints behind the ePort as unavailable. To recover, the user must take corrective action to isolate the ePort, reset the subsystem behind the ePort, clear the ePort interrupt, and re-enable the ePort.

Note: Register references are to the Versal ACAP Register Reference (AM012).

Timeout Counter

The timeout counter starts when the request command from the host has been accepted by the interconnect switch and the transaction is routed to the ePort. When the destination responds to the transaction request (either with data in the case of a read or bus response in the case of a write), the timeout counter is reset and waits for another transaction from the ePort.

If the timeout counter expires during a transaction, the interconnect switch responds back to the transaction initiator and generates a system interrupt.

The clock source for the timeout counter is the PMC_IRO_CLK/4. The PMC_IRO_CLK is internal from the device and comes from a self-starting internal ring oscillator that typically toggles at 400 MHz, which means the typical base timeout clock is 100 MHz. The CPR SWITCH_TIMEOUT_CLK register controls how much this clock is further divided down. The divisor defaults to 100 (0x64), meaning the default timeout clock is 1 MHz.

Interrupt Propagation

The ePort timeout units are distributed across three interconnect networks in the PS: the PMC, LPD, and FPD. The registers that configure the timeouts are located in three separate register modules: LPD_INT_CSR, FPD_INT_CSR, and PMC_INT_CSR.

The ePort timeout interrupts from the FPD and LPD domains are ORed together and routed to the PSM system error accumulator. See PSM Error Status 1.

The ePort timeout interrupts from the PMC domain are ORed together and routed to the PMC system error accumulator. See PMC Error Status 2.

The interrupts do not propagate to the APU processor general interrupt controller (GIC) accumulator.

Frequency Scaling Note

Frequency scaling affects the timeout programming. A slow peripheral bus is more likely to trigger an ePort timeout.

Programming Sequence Example

The egress port timeout programming sequence is as follows:

  1. Program the timeout reference clock. See the CRP SWITCH_TIMEOUT_CTRL register [DIVISOR] bit field [17:8] This clock is shared by all timeout blocks in the PMC, PS, and CPM switches.
  2. Enable the error and timeout interrupt. Set the associated enable bit in the interconnect control and status register (e.g., for the LPD, see the LPD_INT_CSR TIMEOUT_IER register).
  3. Enable the egress port [Timeout_En] bit [0] in the associated interconnect control and status register (e.g., for the LPD RPU 0 programming interface, see the LPD_INT_CSR LPD_AXI_RPU0 ). When disabled, the timeout interrupt for the interface will not occur for incomplete transactions (timeouts).
  4. Monitor the associated interface ePort timeout interrupt bit (e.g., LPD_INT_CSR TIMEOUT_ISR ).

Timeout Instances

There are 20 timeout units in the LPD, 12 in the FPD, and 19 in the PMC.