ePort Timeout

Versal ACAP Technical Reference Manual (AM011)

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1.4 English

The ePort timeout unit monitors the amount of time that a transaction is waiting on the attached block (programming interface or data port). If the amount of time exceeds a threshold, then the timeout unit provides an AXI response back to the initiator and raises an error flag. A timeout condition can be caused by several situations, such as:

  • An unresponsive or misbehaving block that is:
    • Powered-down
    • In its reset state
    • Congested
    • Deadlocked

Timeout Counter

The timeout counter starts when the request command from the master port has been accepted by the interconnect switch and the transaction is routed to the slave port. When the slave responds to the transaction request (either with data in the case of a read or bus response in the case of a write), the timeout counter is reset and waits for another transaction from the master port.

If the timeout counter expires during a transaction, the interconnect switch responds back to the transaction initiator and generates a system interrupt.

Programming Sequence Example

The egress port timeout programming sequence is as follows:

  1. Program the timeout reference clock. See the CRP SWITCH_TIMEOUT_CTRL register [DIVISOR] bit field [17:8] This clock is shared by all timeout blocks in the PMC, PS, and CPM switches.
  2. Enable the error and timeout interrupt. Set the associated enable bit in the interconnect control and status register (e.g., for the LPD, see the LPD_INT_CSR TIMEOUT_IER register).
  3. Enable the egress port [Timeout_En] bit [0] in the associated interconnect control and status register (e.g., for the LPD RPU 0 programming interface, see the LPD_INT_CSR LPD_AXI_RPU0 ). When disabled, the timeout interrupt for the interface will not occur for incomplete transactions (timeouts).
  4. Monitor the associated interface ePort timeout interrupt bit (e.g., LPD_INT_CSR TIMEOUT_ISR ).