APB_ERR (CPM4_CRX) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

APB_ERR (CPM4_CRX) Register Description

Register NameAPB_ERR
Relative Address0x0000000000
Absolute Address 0x00FCA00000 (CPM4_CRX)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionAddress Decode Error Signal (SLVERR) Enable

Alternate register name: REG_CTRL

APB_ERR (CPM4_CRX) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1roRead-only0x0Reserved
slverr_enable 0rwNormal read/write0x0Enable the APB error signal; this is asserted back to the interconnect when the register module programming interface detects an address decode error.
0: keep signal low
1: respond to APB transaction by asserting the SLVERR signal