APB_IDR (CPM4_CRX) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

APB_IDR (CPM4_CRX) Register Description

Register NameAPB_IDR
Relative Address0x0000000010
Absolute Address 0x00FCA00010 (CPM4_CRX)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Disable

Writes: 0: ignored 1: disable an interrupt. This sets the mask register to 1. Alternate register name: IR_DISABLE

APB_IDR (CPM4_CRX) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1roRead-only0x0Reserved
addr_decode_err 0woWrite-only0x0Mask for an address decode error interrupt.