APB_IER (CPM4_CRX) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

APB_IER (CPM4_CRX) Register Description

Register NameAPB_IER
Relative Address0x000000000C
Absolute Address 0x00FCA0000C (CPM4_CRX)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Enable

Writes: 0: ignored 1: enable an interrupt. This sets the mask register to 0. Alternate register name: IR_ENABLE

APB_IER (CPM4_CRX) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:1roRead-only0x0Reserved
addr_decode_err 0woWrite-only0x0Enable for an address decode error interrupt.