APB_ISR (CPM4_CRX) Register Description
| Register Name | APB_ISR |
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| Relative Address | 0x0000000004 |
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| Absolute Address |
0x00FCA00004 (CPM4_CRX)
|
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| Width | 32 |
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| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000000 |
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| Description | Interrupt Status |
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The APB interface decodes the address and if the address does not map to a register, then the address in invalid. When a decode error transaction is detected, writes are ignored and read returns 0. In addition, the interface can optionally assert the error signal (SLVERR) back to the host and/or assert an interrupt. The interrupt status register bits are sticky; they hold their value until cleared by writing a value of 1. 0: not detected 1: detected Alternate register name: IR_STATUS
APB_ISR (CPM4_CRX) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:1 | roRead-only | 0x0 | Reserved |
| addr_decode_err | 0 | wtcReadable, write a 1 to clear | 0x0 | Status for an address decode error interrupt. |