APB_MISC_ISR (CANFD) Register Description
| Register Name | APB_MISC_ISR |
|---|---|
| Relative Address | 0x000000001C |
| Absolute Address |
0x00FF06001C (CANFD0) 0x00FF07001C (CANFD1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Interrupt Status |
Interrupts are generated when an event occurs. The event is recorded in this register. Interrupt bits in the INTR_STAT register can be cleared by writing a 1 to the associated bit in INTR_CLR interrupt clear register. A system interrupt is generated when a bit in the INTR_STAT register is set = 1 and the associated bit in the INTR_EN register is set = 1. Note: In Loopback mode, both TXOK and RXOK bits are set. The RXOK bit is set before the TXOK bit. Software Driver name: XCANFD_ISR Alternate register name: Interrupt_Status_Register
APB_MISC_ISR (CANFD) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TXEWMFLL | 31 | roRead-only | 0x0 | Tx Event Buffer Watermark Full; the buffer is full based on the TxE_WMR [FWM] field value. The bit remains set while the full condition remains true. |
| TXEOFLW | 30 | roRead-only | 0x0 | Tx Event buffer overflow; a Tx Message has been lost. This condition occurs when the controller has successfully transmitted a Message for which the event store is requested but the Tx Event FIFO is full. Note: Also cleared by SW_Reset [CEN] bit. |
| RXMNF | 17 | roRead-only | 0x0 | Rx Match Not Finished; process did not finish until the start of sixth bit in EOF field. The frame was discarded. |
| RXFWMFLL_1 | 16 | roRead-only | 0x0 | RX buffer 1 watermark full; the RX buffer 1 is full based on the TxE_WMR [FWM] field value. The bit remains set while the full condition remains true. |
| RXFOFLW_1 | 15 | roRead-only | 0x0 | RX buffer 1 overflow; a Message has been lost. Occurs when a new Message with ID matching to RX buffer 1 is received and the buffer is full. Note: Also cleared by SW_Reset [CEN] bit. |
| TXCRS | 14 | roRead-only | 0x0 | Tx Cancellation Request Served; request was cleared. |
| TXRRS | 13 | roRead-only | 0x0 | TxBuffer Ready Request Served; request was cleared. |
| RXFWMFLL | 12 | roRead-only | 0x0 | Rx buffer 0 watermark full state; the Rx buffer 0 is full based on the RxBuffer_Watermark [RXFWM] field value. The bit remains set while the full condition remains true. |
| WKUP | 11 | roRead-only | 0x0 | Wake-Up event occured; controller transitioned from sleep mode to normal mode. Note: Also cleared by the SW_Reset [CEN] bit. |
| SLP | 10 | roRead-only | 0x0 | Sleep state entered. Note: Also cleared by the SW_Reset [CEN] bit. |
| BSOFF | 9 | roRead-only | 0x0 | Bus-off state entered. Note: Also cleared by the SW_Reset [CEN] bit. |
| ERROR | 8 | roRead-only | 0x0 | Error occurred during Message transmission re reception. Note: Also cleared by the SW_Reset [CEN] bit. |
| RXFOFLW | 6 | roRead-only | 0x0 | RX buffer 0 Overflow; a Message has been lost. Occurs when a new Message with ID matching to RX buffer 0 is received and the buffer is full. Note: Also cleared by the SW_Reset [CEN] bit. |
| TSCNT_OFLW | 5 | roRead-only | 0x0 | Timestamp Counter Overflow; the counter rolled-over from FFFFh to 0000h. Note: Also cleared by the SW_Reset [CEN] bit. |
| RXOK | 4 | roRead-only | 0x0 | New Message Received successfully and stored in the RX buffer 0 or 1. Note: Also cleared by the SW_Reset [CEN] bit. |
| BSFRD | 3 | roRead-only | 0x0 | Bus-off Recovery Done; controller recovered from bus-off state. Note: Also cleared by the SW_Reset [CEN] bit. |
| PEE | 2 | roRead-only | 0x0 | Protocol Exception Event detected in receiver. Note: Also cleared by the SW_Reset [CEN] bit. |
| TXOK | 1 | roRead-only | 0x0 | Message Transmission Successful. Note: Also cleared by the SW_Reset [CEN] bit. |
| ARBLST | 0 | roRead-only | 0x0 | Arbitration Lost During Message Transmission. Note: Also cleared by the SW_Reset [CEN] bit. |