AXIBar_Attr_3 (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

AXIBar_Attr_3 (CPM4_DMA_ATTR) Register Description

Register NameAXIBar_Attr_3
Relative Address0x0000000158
Absolute Address 0x00FCA70158 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
Descriptionbar attributes
[0]: relaxed read txn.
base[0] and higaddr[0] for this bar must also be set

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_axibar_attr_3

AXIBar_Attr_3 (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr 2:0rwNormal read/write0x0bar attributes
[0]: relaxed read txn.
base[0] and higaddr[0] for this bar must also be set