AXIBar_Base_2_H (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

AXIBar_Base_2_H (CPM4_DMA_ATTR) Register Description

Register NameAXIBar_Base_2_H
Relative Address0x0000000118
Absolute Address 0x00FCA70118 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionAXI to PCIe bar base

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_axibar_base_2_h

AXIBar_Base_2_H (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x0AXI to PCIe bar base