AXI_slv_XDMA_Base_Addr_L (CPM4_DMA_ATTR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

AXI_slv_XDMA_Base_Addr_L (CPM4_DMA_ATTR) Register Description

Register NameAXI_slv_XDMA_Base_Addr_L
Relative Address0x00000000C0
Absolute Address 0x00FCA700C0 (CPM4_DMA_ATTR)
Width32
TyperwNormal read/write
Reset Value0x00000000
Description64K space - base determined by PS. This is the base address of the XDMA registers.

This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_axi_slv_xdma_base_addr_l

AXI_slv_XDMA_Base_Addr_L (CPM4_DMA_ATTR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr31:0rwNormal read/write0x064K space - base determined by PS. This is the base address of the XDMA registers.