CANFD Module

Versal Adaptive SoC Register Reference (AM012)

Document ID

AM012

Release Date

2023-08-29

Revision

1.3

CANFD Module Description

Module Name	CANFD Module
Modules of this Type	CANFD0, CANFD1
Base Address	0x00FF060000 (CANFD0) 0x00FF070000 (CANFD1)
Description	CAN FD Controller

CANFD Module Register Summary

Register Name	Address	Width	Type	Reset Value	Description
SW_Reset	0x0000000000	2	mixedMixed types. See bit-field details.	0x00000000	Software Reset and Enable Control
Mode_Select	0x0000000004	16	rwNormal read/write	0x00000000	Mode Select
ArbPhase_BaudRate	0x0000000008	8	rwNormal read/write	0x00000000	Arbitration Phase Baud Rate Prescaler
ArbPhase_BitTiming	0x000000000C	23	rwNormal read/write	0x00000000	Arbitration Phase Bit Timing
Error_Count	0x0000000010	16	roRead-only	0x00000000	Error Count
Error_Status	0x0000000014	12	wtcReadable, write a 1 to clear	0x00000000	Error Status
Status	0x0000000018	23	roRead-only	0x00000001	CAN Bus, Mode, and Error Status
APB_MISC_ISR	0x000000001C	32	roRead-only	0x00000000	Interrupt Status
APB_MISC_IER	0x0000000020	32	rwNormal read/write	0x00000000	Interrupt Enable
APB_MISC_ICR	0x0000000024	32	woWrite-only	0x00000000	Interrupt Clear
Timestamp	0x0000000028	32	mixedMixed types. See bit-field details.	0x00000000	Timestamp Clear and count
DataPhase_BaudRate	0x0000000088	17	rwNormal read/write	0x00000000	Data Phase Baud Rate Prescaler
DataPhase_BitTiming	0x000000008C	20	rwNormal read/write	0x00000000	Data Phase Bit Timing
TxBuff_Ready_Req	0x0000000090	32	rwsoRead/write, set only	0x00000000	TxBuffer Ready Request
TxBuff_Ready_Req_Intr_En	0x0000000094	32	rwNormal read/write	0x00000000	TX Buffer Ready Request Interrupt Enables
Tx_Buff_Cancel_Req	0x0000000098	32	rwsoRead/write, set only	0x00000000	Tx Message Cancellation Request
TxBuff_Cancel_Req_Intr_En	0x000000009C	32	rwNormal read/write	0x00000000	Tx Message Cancellation Request Interrupt Enable
TxEvent_FIFO_Status	0x00000000A0	14	mixedMixed types. See bit-field details.	0x00000000	Tx Event Buffer Status
TxEvent_FIFO_Watermark	0x00000000A4	5	rwNormal read/write	0x0000000F	Tx Event FIFO Watermark
AF_Control	0x00000000E0	32	rwNormal read/write	0x00000000	Acceptance Filter Enables
RxBuff_Status	0x00000000E8	31	mixedMixed types. See bit-field details.	0x00000000	Rx Buffer Status
RxBuff_Watermark	0x00000000EC	22	rwNormal read/write	0x001F0F0F	Rx Buffer Watermark
TxBuff_ID_Msg_n	0x0000000100	32	rwNormal read/write	0x00000000	32 ID regs for TxBuffer msgs 0 to 31 at 0x0100, 0x0148, etc (0x48 step)
TxBuff_DLC_Msg_n	0x0000000104	32	rwNormal read/write	0x00000000	32 DLC regs for TxBuffer msgs 0 to 31 at 0x0104, 0x014C, etc (0x48 step)
TxBuff_DW00_Msg_n	0x0000000108	32	rwNormal read/write	0x00000000	32 TxBuffer dw_0 regs for msgs 0 to 31 at 0x0108, 0x0150, etc (0x48 step)
TxBuff_DW01_Msg_n	0x000000010C	32	rwNormal read/write	0x00000000	32 TxBuffer dw_1 regs for msgs 0 to 31 at 0x010C, 0x0154, etc (0x48 step)
TxBuff_DW02_Msg_n	0x0000000110	32	rwNormal read/write	0x00000000	32 TxBuffer dw_2 regs for msgs 0 to 31 at 0x0110, 0x0158, etc (0x48 step)
TxBuff_DW03_Msg_n	0x0000000114	32	rwNormal read/write	0x00000000	32 TxBuffer dw_3 regs for msgs 0 to 31 at 0x0114, 0x015C, etc (0x48 step)
TxBuff_DW04_Msg_n	0x0000000118	32	rwNormal read/write	0x00000000	32 TxBuffer dw_4 regs for msgs 0 to 31 at 0x0118, 0x0160, etc (0x48 step)
TxBuff_DW05_Msg_n	0x000000011C	32	rwNormal read/write	0x00000000	32 TxBuffer dw_5 regs for msgs 0 to 31 at 0x011C, 0x0164, etc (0x48 step)
TxBuff_DW06_Msg_n	0x0000000120	32	rwNormal read/write	0x00000000	32 TxBuffer dw_6 regs for msgs 0 to 31 at 0x0120, 0x0168, etc (0x48 step)
TxBuff_DW07_Msg_n	0x0000000124	32	rwNormal read/write	0x00000000	32 TxBuffer dw_7 regs for msgs 0 to 31 at 0x0124, 0x016C, etc (0x48 step)
TxBuff_DW08_Msg_n	0x0000000128	32	rwNormal read/write	0x00000000	32 TxBuffer dw_8 regs for msgs 0 to 31 at 0x0128, 0x0170, etc (0x48 step)
TxBuff_DW09_Msg_n	0x000000012C	32	rwNormal read/write	0x00000000	32 TxBuffer dw_9,regs for msgs 0 to 31 at 0x012C, 0x0174, etc (0x48 step)
TxBuff_DW10_Msg_n	0x0000000130	32	rwNormal read/write	0x00000000	32 TxBuffer dw_10 regs for msgs 0 to 31 at 0x0130, 0x0178, etc (0x48 step)
TxBuff_DW11_Msg_n	0x0000000134	32	rwNormal read/write	0x00000000	32 TxBuffer dw_11 regs for msgs 0 to 31 at 0x0134, 0x017C, etc (0x48 step)
TxBuff_DW12_Msg_n	0x0000000138	32	rwNormal read/write	0x00000000	32 TxBuffer dw_12 regs for msgs 0 to 31 at 0x0138, 0x0180, etc (0x48 step)
TxBuff_DW13_Msg_n	0x000000013C	32	rwNormal read/write	0x00000000	32 TxBuffer dw_13 regs for msgs 0 to 31 at 0x013C, 0x0184, etc (0x48 step)
TxBuff_DW14_Msg_n	0x0000000140	32	rwNormal read/write	0x00000000	32 TxBuffer dw_14 regs for msgs 0 to 31 at 0x0140, 0x0188, etc (0x48 step)
TxBuff_DW15_Msg_n	0x0000000144	32	rwNormal read/write	0x00000000	32 TxBuffer dw_15 regs for msgs 0 to 31 at 0x0144, 0x018C, etc (0x48 step)
AF_Mask_Reg_n	0x0000000A00	32	rwNormal read/write	0x00000000	32 Acceptance Filter Mask regs 0 to 31 at 0x0A00, 0x0A08, etc (0x08 step)
AF_ID_Reg_n	0x0000000A04	32	rwNormal read/write	0x00000000	32 Acceptance Filter ID regs 0 to 31 at 0x0A04, 0x0A0C, etc (0x08 step)
TxEvent_ID_Reg_n	0x0000002000	32	roRead-only	0x00000000	32 ID regs for TxEvent msgs 0 to 31 at 0x2000, 0x2008, etc (0x08 step)
TxEvent_DLC_Reg_n	0x0000002004	32	roRead-only	0x00000000	32 DLC regs for TxEvent msgs 0 to 31 at 0x2004, 0x200C, etc (0x08 step)
RxBuff0_ID_Msg_n	0x0000002100	32	roRead-only	0x00000000	64 RxBuffer_0 ID regs for msgs 0 to 63 at 0x2100, 0x2148, etc (0x48 step)
RxBuff0_DLC_Msg_n	0x0000002104	32	roRead-only	0x00000000	64 RxBuffer_0 DLC regs for msgs 0 to 63 at 0x2104, 214C, etc (0x48 step)
RxBuff0_DW00_Msg_n	0x0000002108	32	roRead-only	0x00000000	64 dw_0 regs for RxBuffer_0 msgs 0 to 63 at 0x2108, 0x2150, etc (0x48 step)
RxBuff0_DW01_Msg_n	0x000000210C	32	roRead-only	0x00000000	64 dw_1 regs for RxBuffer_0 msgs 0 to 63 at 0x210C, 0x2154, etc (0x48 step)
RxBuff0_DW02_Msg_n	0x0000002110	32	roRead-only	0x00000000	64 dw_2 regs for RxBuffer_0 msgs 0 to 63 at 0x2110, 0x2158, etc (0x48 step)
RxBuff0_DW03_Msg_n	0x0000002114	32	roRead-only	0x00000000	64 dw_3 regs for RxBuffer_0 msgs 0 to 63 at 0x2114, 0x215C, etc (0x48 step)
RxBuff0_DW04_Msg_n	0x0000002118	32	roRead-only	0x00000000	64 dw_4 regs for RxBuffer_0 msgs 0 to 63 at 0x2118, 0x2160, etc (0x48 step)
RxBuff0_DW05_Msg_n	0x000000211C	32	roRead-only	0x00000000	64 dw_5 regs for RxBuffer_0 msgs 0 to 63 at 0x211C, 0x2164, etc (0x48 step)
RxBuff0_DW06_Msg_n	0x0000002120	32	roRead-only	0x00000000	64 dw_6 regs for RxBuffer_0 msgs 0 to 63 at 0x2120, 0x2168, etc (0x48 step)
RxBuff0_DW07_Msg_n	0x0000002124	32	roRead-only	0x00000000	64 dw_7 regs for RxBuffer_0 msgs 0 to 63 at 0x2124, 0x216C, etc (0x48 step)
RxBuff0_DW08_Msg_n	0x0000002128	32	roRead-only	0x00000000	64 dw_8 regs for RxBuffer_0 msgs 0 to 63 at 0x2128, 0x2170, etc (0x48 step)
RxBuff0_DW09_Msg_n	0x000000212C	32	roRead-only	0x00000000	64 dw_9 regs for RxBuffer_0 msgs 0 to 63 at 0x212C, 0x2174, etc (0x48 step)
RxBuff0_DW10_Msg_n	0x0000002130	32	roRead-only	0x00000000	64 dw_10 regs for RxBuffer_0 msgs 0 to 63 at 0x2130, 0x2178, etc (0x48 step)
RxBuff0_DW11_Msg_n	0x0000002134	32	roRead-only	0x00000000	64 dw_11 regs for RxBuffer_0 msgs 0 to 63 at 0x2134, 0x217C, etc (0x48 step)
RxBuff0_DW12_Msg_n	0x0000002138	32	roRead-only	0x00000000	64 dw_12 regs for RxBuffer_0 msgs 0 to 63 at 0x2138, 0x2180, etc (0x48 step)
RxBuff0_DW13_Msg_n	0x000000213C	32	roRead-only	0x00000000	64 dw_13 regs for RxBuffer_0 msgs 0 to 63 at 0x213C, 0x2184, etc (0x48 step)
RxBuff0_DW14_Msg_n	0x0000002140	32	roRead-only	0x00000000	64 dw_14 regs for RxBuffer_0 msgs 0 to 63 at 0x2140, 0x2188, etc (0x48 step)
RxBuff0_DW15_Msg_n	0x0000002144	32	roRead-only	0x00000000	64 dw_15 regs for RxBuffer_0 msgs 0 to 63 at 0x2144, 0x218C, etc (0x48 step)
RxBuff1_ID_Msg_n	0x0000004100	32	roRead-only	0x00000000	64 ID regs for RxBuffer_1 msgs 0 to 63 at 0x4100, 0x4148, etc (0x48 step)
RxBuff1_DLC_Msg_n	0x0000004104	32	roRead-only	0x00000000	64 DLC regs for RxBuffer_1 msgs 0 to 63 at 0x4104, 0x0414C, etc (0x48 step)
RxBuff1_DW00_Msg_n	0x0000004108	32	roRead-only	0x00000000	64 dw_0 regs for RxBuffer_1 msgs 0 to 63 at 0x4108, 0x4150, etc (0x48 step)
RxBuff1_DW01_Msg_n	0x000000410C	32	roRead-only	0x00000000	64 dw_1 regs for RxBuffer_1 msgs 0 to 63 at 0x410C, 0x4154, etc (0x48 step)
RxBuff1_DW02_Msg_n	0x0000004110	32	roRead-only	0x00000000	64 dw_2 regs for RxBuffer_1 msgs 0 to 63 at 0x4110, 0x4158, etc (0x48 step)
RxBuff1_DW03_Msg_n	0x0000004114	32	roRead-only	0x00000000	64 dw_3 regs for RxBuffer_1 msgs 0 to 63 at 0x4114, 0x415C, etc (0x48 step)
RxBuff1_DW04_Msg_n	0x0000004118	32	roRead-only	0x00000000	64 dw_4 regs for RxBuffer_1 msgs 0 to 63 at 0x4118, 0x4160, etc (0x48 step)
RxBuff1_DW05_Msg_n	0x000000411C	32	roRead-only	0x00000000	64 dw_5 regs for RxBuffer_1 msgs 0 to 63 at 0x411C, 0x4164, etc (0x48 step)
RxBuff1_DW06_Msg_n	0x0000004120	32	roRead-only	0x00000000	64 dw_6 regs for RxBuffer_1 msgs 0 to 63 at 0x4120, 0x4168, etc (0x48 step)
RxBuff1_DW07_Msg_n	0x0000004124	32	roRead-only	0x00000000	64 dw_7 regs for RxBuffer_1 msgs 0 to 63 at 0x4124, 0x416C, etc (0x48 step)
RxBuff1_DW08_Msg_n	0x0000004128	32	roRead-only	0x00000000	64 dw_8 regs for RxBuffer_1 msgs 0 to 63 at 0x4128, 0x4170, etc (0x48 step)
RxBuff1_DW09_Msg_n	0x000000412C	32	roRead-only	0x00000000	64 dw_9 regs for RxBuffer_1 msgs 0 to 63 at 0x412C, 0x4174, etc (0x48 step)
RxBuff1_DW10_Msg_n	0x0000004130	32	roRead-only	0x00000000	64 dw_10 regs for RxBuffer_1 msgs 0 to 63 at 0x4130, 0x4178, etc (0x48 step)
RxBuff1_DW11_Msg_n	0x0000004134	32	roRead-only	0x00000000	64 dw_11 regs for RxBuffer_1 msgs 0 to 63 at 0x4134, 0x417C, etc (0x48 step)
RxBuff1_DW12_Msg_n	0x0000004138	32	roRead-only	0x00000000	64 dw_12 regs for RxBuffer_1 msgs 0 to 63 at 0x4138, 0x4180, etc (0x48 step)
RxBuff1_DW13_Msg_n	0x000000413C	32	roRead-only	0x00000000	64 dw_13 regs for RxBuffer_1 msgs 0 to 63 at 0x413C, 0x4184, etc (0x48 step)
RxBuff1_DW14_Msg_n	0x0000004140	32	roRead-only	0x00000000	64 dw_14 regs for RxBuffer_1 msgs 0 to 63 at 0x4140, 0x4188, etc (0x48 step)
RxBuff1_DW15_Msg_n	0x0000004144	32	roRead-only	0x00000000	64 dw_15 regs for RxBuffer_1 msgs 0 to 63 at 0x4144, 0x418C, etc (0x48 step)