CFU_CSR Module

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

CFU_CSR Module Description

Module NameCFU_CSR Module
Modules of this TypeCFU_CSR
Base Address0x00F12B0000 (CFU_CSR)
DescriptionCFU Configuration Unit (aka CFU_APB)

CFU_CSR Module Register Summary

Register NameAddressWidthTypeReset ValueDescription
CFU_ISR0x000000000032mixedMixed types. See bit-field details.0x00000000Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.
CFU_IMR0x000000000432mixedMixed types. See bit-field details.0x000003FFInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. HW reset always default to 1. (erg script ignores reset_value column)
CFU_IER0x000000000832mixedMixed types. See bit-field details.0x00000000Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0)
CFU_IDR0x000000000C32mixedMixed types. See bit-field details.0x00000000Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1)
CFU_ITR0x000000001032mixedMixed types. See bit-field details.0x00000000Interrupt Trigger Register. A write of one to this location will the interrupt. (mainly for testing)
CFU_PROTECT0x0000000014 1rwNormal read/write0x00000001CFU write protect register
CFU_FGCR0x000000001832mixedMixed types. See bit-field details.0x00000000Fabric global signal register.
CFU_CTL0x000000001C32mixedMixed types. See bit-field details.0x00000000CFU Control Register, requires CFU_MASK
CFU_MASK0x000000002832rwNormal read/write0x00000000CFU register bit level masking (Apply to CFU_CTL and CFU_FGCR only)
CFU_CRC_EXPECT0x000000002C32rwNormal read/write0x00000000Expected CRC32 for CFI segment of DPI/bitstream.
CFU_CFRAME_LEFT_T00x000000006032mixedMixed types. See bit-field details.0x00000000Type-0 frame number to the left of cframe
CFU_CFRAME_LEFT_T10x000000006432mixedMixed types. See bit-field details.0x00000000Type-1 frame number to the left of cframe
CFU_CFRAME_LEFT_T20x000000006832mixedMixed types. See bit-field details.0x00000000Type-2 frame number to the left of cframe
CFU_ROW_RANGE0x000000006C32mixedMixed types. See bit-field details.0x00000000Number of CFrame rows in the device
CFU_STATUS0x000000010032mixedMixed types. See bit-field details.0x00000000ATB Sideband Signals
CFU_QWORD_CNT0x000000010832roRead-only0x00000000number of AXI qwords received from AXI stream port for debugging
CFU_CRC_LIVE0x000000010C32roRead-only0x00000000accumulated CRC from stream port.
CFU_PENDING_READ_CNT0x000000011032mixedMixed types. See bit-field details.0x00000000frame read qword count
CFU_FDRI_CNT0x000000011432roRead-only0x00000000FDRI_CNT value