| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:16 | razRead as zero | 0x0 | reserved for future use |
| gsr_gsc | 15 | rwNormal read/write | 0x0 | 1 to enable gsr fabric input to respect gsc=1 to not disturb static region. By default, gsr_gsc=0, gsr force en_globs=1 to ignore gsc=1, so it wipes out entire PL region during security reset event |
| slverr_en | 14 | rwNormal read/write | 0x0 | Enable or disable APB SLVERR during address decode failure. 0: SLVERR is disabled. For request address: Writes are ignored. Read returns 0. 1: SLVERR is enabled. For request address, SLVERR is asserted. Writes are ignored and read returns 0. |
| crc32_reset | 13 | rwNormal read/write | 0x0 | 1 to reset CFU_CRC_LIVE to 0 |
| axi_error_en | 12 | rwNormal read/write | 0x0 | 1=enable generating AXI slave error if AXI data error (crc8, crc32) or CFRAME error detected. by default CFU doesn't generate AXI slave error. |
| flush_axi | 11 | rwNormal read/write | 0x0 | force AXI to generate response. In case, CFI is blocked but no error. |
| ssi_per_slr_pr | 10 | rwNormal read/write | 0x0 | 1=enable SSI device per SLR partial reconfig for PL. Meaning PL global signals (ghigh_b, grestore, gwe) are no longer wired-OR together |
| gcap_clk_en | 9 | rwNormal read/write | 0x0 | 1=use gcap_clk to pipeline gcap. 0=use gcap directly. |
| status_sync_disable | 8 | rwNormal read/write | 0x0 | This bit no longer controls anything, since CFU APB_CLK and CFI_CLK are now synchronous. 1=disable APB status synchronization. Multi-bits counter or FSM from CFU clock domain, must be synchronized to APB clock to read reliably. If disabled (to save power etc., not recommended), then the CFU domain status is directly sent to APB read, it could catch transient state value though. |
| ignore_cfi_error | 7 | rwNormal read/write | 0x0 | 1=ignore cfi error. When cfi_error is asserted, all pending transactions are dropped, and CFI is stoppped. In order to readback CFRAME status, FW interrupt routing assert cframe_disable=1 first, then assert cfi_local_reset (also clear Axi switch, DMA as needed) to clean up previous pending transaction inside CFU. Lastly set ignore_cfi_error=1 to allow CFRAME ISR/IMR/IER/IDR to be accessed. |
| cframe_disable | 6 | rwNormal read/write | 0x0 | 1=disable CFRAME engine. This bit is used to cleanly shutdown cframe engine before applying cfi_local_reset to avoid undesired asynchronous transtion noise. |
| qword_cnt_reset | 5 | rwNormal read/write | 0x0 | 1=reset CFU_QWORD_CNT (number of QWORD received from stream port, debugging feature) |
| crc8_disable | 4 | rwNormal read/write | 0x0 | 1=disable packet header crc8 check for ease of. |
| crc32_check | 3 | rwNormal read/write | 0x0 | rising edge trigger CRC32 check for stream data. Live CRC32 is reset to 0 |
| decompress | 2 | rwNormal read/write | 0x0 | 1=enable decompress. |
| seu_go | 1 | rwNormal read/write | 0x0 | Controls CFRAME SEU Engine stop/go |
| cfi_local_reset | 0 | rwNormal read/write | 0x0 | CFU/CFI local reset, only reset FSM, flush pipeline etc. But retain programming registers and debugging status. Cframe_disable should be set prior to assert cfi_local_reset to ensure orderly shutdown CFRAME engine. |