CFU_FGCR (CFU_CSR) Register Description
| Register Name | CFU_FGCR |
|---|---|
| Relative Address | 0x0000000018 |
| Absolute Address | 0x00F12B0018 (CFU_CSR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Fabric global signal register. |
Requires CFU_MASK and unlocked CFU_PROTECT.
CFU_FGCR (CFU_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:15 | razRead as zero | 0x0 | reserved for future use |
| gclk_cal | 14 | rwNormal read/write | 0x0 | Active clock de-skew calibration. BUFG will use MCLK during calibration. |
| sc_hbc_trigger | 13 | rwNormal read/write | 0x0 | hard block scan clear trigger |
| glow | 12 | rwNormal read/write | 0x0 | testing feature to force all input to inter-connect low |
| gpwrdwn | 11 | rwNormal read/write | 0x0 | Global power down.Triggered by device overtemp alarm in AMS |
| gcap | 10 | rwNormal read/write | 0x0 | CLE/Laguna/BRAM DFF state capture |
| gscwe | 9 | rwNormal read/write | 0x0 | 1=write GSC bits only in a frame. 0=write all bits in a frame |
| ghigh_b | 8 | rwNormal read/write | 0x0 | Forces block outputs that drive interconnect to 1. This ensures a known stable value during configuration events. This helps reduce the possibility of contention. |
| gmc_b | 7 | rwNormal read/write | 0x0 | The Gate Memory Cell signal is used in some blocks to gate the memory cell outputs during the configuration process. Examples blocks are HDIO and PCIE |
| gwe | 6 | rwNormal read/write | 0x0 | Disables clocking of synchronous elements in functional blocks. Synchronous elements must not change state when GWE is not asserted. |
| grestore | 5 | rwNormal read/write | 0x0 | Initializes synchronous elements in functional blocks to a desired state. This signal is normally pulsed near the end of a configuration or PR event |
| gts_cfg_b | 4 | rwNormal read/write | 0x0 | Forces the HRIO and HPIO drivers to be tristated. Also used to gate external feedback loop function in CMT |
| glutmask | 3 | rwNormal read/write | 0x0 | This signal is used to mask readback data when reading frames which contain user-modifiable memory cells. This includes LUTRAM data, SRL data, and DRP (or APB3 data). This masking function is required for correct function of SEU readback, since the ECC values cannot be re-calculated on continuously changing frame data values. The readback value of a memory cell masked by GLUTMASK is 0. Note that GLUTMASK also prevents writes to the affected memory cells so GLUTMASK must be de-asserted prior to Partial Reconfiguration of regions |
| en_globs_b | 2 | rwNormal read/write | 0x0 | Forces Global Signal Control logic to ignore the state of the Global Signal Control (GSC) memory cells. In other words, if en_glob_b is asserted, the global signals always take effect. (was en_globs) |
| eos | 1 | rwNormal read/write | 0x0 | end of startup |
| init_complete | 0 | rwNormal read/write | 0x0 | houseclean is completed. |