CFU_ISR (CFU_CSR) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

CFU_ISR (CFU_CSR) Register Description

Register NameCFU_ISR
Relative Address0x0000000000
Absolute Address 0x00F12B0000 (CFU_CSR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1.

CFU_ISR (CFU_CSR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:10razRead as zero0x0reserved for future use
usr_gts_event 9wtcReadable, write a 1 to clear0x0reset by por only. ISR for fabric GTS event. GTS tri-state all PL HDIO
usr_gsr_event 8wtcReadable, write a 1 to clear0x0reset by por only. ISR for fabric GSR event. GSR clear entire fabric user visible state
slverr 7wtcReadable, write a 1 to clear0x0RPU Lockstep Errors from RPU0. The Lockstep error is not initialized until RPU clock is enabled; therefore, error outcomes are masked by default and are expected to be unmasked after processor clock is enabled and before its reset is released.
decomp_error 6wtcReadable, write a 1 to clear0x0reset by por only. ISR for decompression errors. At decompress rising edge, CFU AXI wfifo is not empty. While decompress=1, there is unexpected AXI read or none-stream AXI write, at decompress falling edge, there is residue inside decompression engine.
bad_cfi_packet 5wtcReadable, write a 1 to clear0x0reset by por only. ISR for bad CFI packet from stream keyhole aperture, or r/w to reserved space, or write to FDRO space, or read to SFR space, or read to stream space, read CFRAME reg in the middle of FDRI, or none-stream and none-FDRI access in the middle of FDRI.
axi_align_error 4wtcReadable, write a 1 to clear0x0reset by por only. ISR for axi alignment error (x32 expect word addr 0, 1, 2, 3.
x64 expect dword address 0, 1)
cfi_row_error 3wtcReadable, write a 1 to clear0x0reset by por only. ISR for accessing out of range row
crc32_error 2wtcReadable, write a 1 to clear0x0reset by por only. ISR for bitstream crc32 error
crc8_error 1wtcReadable, write a 1 to clear0x0reset by por only. ISR for bitstream packet header crc8 error
seu_endofcalib 0wtcReadable, write a 1 to clear0x0reset by por only. ISR for seu_endofcalib. This is AND of all cframe seu_endofcalib, may used by Safety