| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31 | razRead as zero | 0x0 | reserved for future use |
| seu_write_error | 30 | roRead-only | 0 | write to cframe while seu_go=1 error. (expect to set seu_go=0, then write to cframe) |
| frcnt_error | 29 | roRead-only | 0 | read non-FDRO while frcnt !=0 (meaning there are pending FDRO reads to be completed first) |
| rsvd_error | 28 | roRead-only | 0 | read or write to reserved aperture error |
| fdro_error | 27 | roRead-only | 0 | write to read only FDRO aperture error |
| fdri_error | 26 | roRead-only | 0 | Invalid AXI address during FDRI phase error |
| fdri_read_error | 25 | roRead-only | 0 | AXI read in the middle of FDRI phase error |
| read_fdri_error | 24 | roRead-only | 0 | read to write only MM FDRI aperture error |
| read_sfr_error | 23 | roRead-only | 0 | read to write only SFR aperture error |
| read_stream_error | 22 | roRead-only | 0 | read to write only stream aperture error |
| unknown_stream_pkt | 21 | roRead-only | 0 | unknown stream packet error |
| usr_gts | 20 | roRead-only | 0 | use gts live state |
| usr_gsr | 19 | roRead-only | 0 | usr_gsr live state |
| axi_bad_wstrb | 18 | roRead-only | 0 | AXI un-support wstrb (not 32,64 or 128 aligned), or wstrb out of sequence |
| axi_bad_ar_size | 17 | roRead-only | 0 | AXI un-supported ar_size. (x32, x64, x128 only) |
| axi_bad_aw_size | 16 | roRead-only | 0 | AXI un-supported aw_size. (x32, x64, x128 only) |
| axi_bad_araddr | 15 | roRead-only | 0 | AXI araddr misalign error |
| axi_bad_awaddr | 14 | roRead-only | 0 | AXI awaddr misalign error |
| scan_clear_pass | 13 | roRead-only | 0 | hard block scan clear and mbist pass. 0 means error, must qualified by scan_clear_done=1. |
| hc_sec_error | 12 | roRead-only | 0 | read CRAM before houseclean security violation. Requires POR to clear the flag (non-recoverable error) |
| ghigh_b_ishigh | 11 | roRead-only | 0 | ghigh_b is high for entire chip after propagation |
| ghigh_b_islow | 10 | roRead-only | 0 | ghigh_b is low for entire chip after propagation |
| gmc_b_ishigh | 9 | roRead-only | 0 | gmc_b is high for entire chip after propagation |
| gmc_b_islow | 8 | roRead-only | 0 | gmc_b is low for entire chip after propagation |
| gpwrdwn_b_ishigh | 7 | roRead-only | 0 | gpwrdwn_b is high for entire chip after propagation |
| cfi_seu_crc_error | 6 | roRead-only | 0 | cfi_seu_crc_error |
| cfi_seu_ecc_error | 5 | roRead-only | 0 | cfi_seu_ecc_error |
| cfi_seu_heartbeat | 4 | roRead-only | 0 | cfi_seu_heartbeat |
| scan_clear_done | 3 | roRead-only | 0 | hard block scan clear and mbist complete. Was sc_hbc_complete |
| hc_complete | 2 | roRead-only | 0 | type 0/1/2 houseclean (which is the last step) is completed. |
| cfi_cframe_busy | 1 | roRead-only | 0 | cfi_cframe_busy |
| cfu_stream_busy | 0 | roRead-only | 0 | Indicate CFU/CFI is the the middle of receiving stream data. Cfu_stream_busy goes high when CFU_START marker packet is received. Cfu_stream_busy goes low when CFU_END marker packet is received. |