CONFIG_0 (APU_DUAL_CSR) Register Description
| Register Name | CONFIG_0 |
|---|---|
| Relative Address | 0x0000000020 |
| Absolute Address | 0x00FD5C0020 (APU_DUAL_CSR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000303 |
| Description | CPU Core Configuration |
CONFIG_0 (APU_DUAL_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CFGTE | 25:24 | rwNormal read/write | 0x0 | Drives the A72MP CFGTE signals that determine the individual core control of the endianness configuration at reset. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. The upper bit is for CPU core 1; the lower bit is for CPU core 0. |
| CFGEND | 17:16 | rwNormal read/write | 0x0 | Drives the A72MP CFGEND signals that determine the individual core control of the location of the exception vectors at reset. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. The upper bit is for CPU core 1; the lower bit is for CPU core 0. |
| VINITHI | 9:8 | rwNormal read/write | 0x3 | Drives the A72MP VINITHI signals that determine the individual core control of the default exception handling state. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. The upper bit is for CPU core 1; the lower bit is for CPU core 0. |
| AA64nAA32 | 1:0 | rwNormal read/write | 0x3 | Drives the A72MP AA64nAA32 signals that determine the individual core register width state. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. The upper bit is for CPU core 1; the lower bit is for CPU core 0. |