CONFIG_1 (APU_DUAL_CSR) Register Description
| Register Name | CONFIG_1 |
|---|---|
| Relative Address | 0x0000000024 |
| Absolute Address | 0x00FD5C0024 (APU_DUAL_CSR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | L2 Configuration |
CONFIG_1 (APU_DUAL_CSR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| L1RSTDISABLE | 28 | rwNormal read/write | 0x0 | Drives the A72MP DGBL1RSTDISABLE signal that disables L1 data cache and L2 snoop tag RAM automatic invalidate on reset functionality. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. This bit is for all CPU cores and L2. |
| CP15SDISABLE | 1:0 | rwNormal read/write | 0x0 | Drives the A72MP CP15SDISABLE signals that disable write access to some Secure CP15 registers. For details, refer to ARM Cortex-A72 MPCore Processor Technical Reference Manual. The upper bit is for CPU core 1; the lower bit is for CPU core 0. |