| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:27 | roRead-only | 0x0 | reserved |
| POST_SRC | 26:24 | rwNormal read/write | 0x0 | reserved, write 0 to select REF_CLK |
| Reserved | 23 | roRead-only | 0x0 | reserved |
| PRE_SRC | 22:20 | rwNormal read/write | 0x0 | reserved, write 0 to select REF_CLK |
| Reserved | 19:18 | roRead-only | 0x0 | reserved |
| FBDIV | 15:8 | rwNormal read/write | 0x48 | The integer portion of the feedback divider to the PLL |
| Reserved | 7:4 | roRead-only | 0x0 | reserved |
| BYPASS | 3 | rwNormal read/write | 0x1 | Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. After a change, this signal may be toggled again only after 4 cycles of the old clock followed by 6 cycles of the new clock. |
| Reserved | 2:1 | roRead-only | 0x0 | reserved |
| RESET | 0 | rwNormal read/write | 0x1 | Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS. |