CPLL_STATUS (CPM4_CRX) Register

Versal Adaptive SoC Register Reference (AM012)

Document ID
AM012
Release Date
2023-08-29
Revision
1.3

CPLL_STATUS (CPM4_CRX) Register Description

Register NameCPLL_STATUS
Relative Address0x0000000050
Absolute Address 0x00FCA00050 (CPM4_CRX)
Width 8
TyperoRead-only
Reset Value0x00000004
DescriptionCPLL Status

Alternate register name: PLL_STATUS

CPLL_STATUS (CPM4_CRX) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved 7:3roRead-only0x0reserved
CPLL_STABLE 2roRead-only0x1PLL is stable, which means it is either locked or in bypass
Reserved 1roRead-only0x0reserved
CPLL_LOCK 0roRead-only0x0PLL is locked