| Register Name | Address | Width | Type | Reset Value | Description |
|---|
| APB_ERR | 0x0000000000 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Address Decode Error Signal (SLVERR) Enable |
| APB_ISR | 0x0000000004 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Status |
| APB_IMR | 0x0000000008 | 32 | roRead-only | 0x00000001 | Interrupt Mask |
| APB_IER | 0x000000000C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Enable |
| APB_IDR | 0x0000000010 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Disable |
| WPROT | 0x0000000030 | 1 | rwNormal read/write | 0x00000000 | CRF Write Protection Control |
| CPLL_CTRL | 0x0000000040 | 32 | mixedMixed types. See bit-field details. | 0x00004809 | CPM PLL Clock Control (CPLL) |
| CPLL_CFG | 0x0000000044 | 32 | mixedMixed types. See bit-field details. | 0x02000000 | Helper data. Values are to be looked up in a table from Data Sheet based on FBDIV value |
| CPLL_STATUS | 0x0000000050 | 8 | roRead-only | 0x00000004 | CPLL Status |
| CPM_CORE_REF_CTRL | 0x0000000100 | 32 | mixedMixed types. See bit-field details. | 0x02002500 | Enable and Divider controls for cpm_core_clk. All CCB features (CMN, L2, Address Remap) run on this clock |
| CPM_LSBUS_REF_CTRL | 0x0000000104 | 32 | mixedMixed types. See bit-field details. | 0x02002500 | Enable and Divider controls for cpm_lsbus_clk. All configuration and interrupt registers run on this clock |
| CPM_DBG_REF_CTRL | 0x0000000108 | 32 | mixedMixed types. See bit-field details. | 0x02002500 | Enable and Divider controls for cpm_dbg_clk. All SOC Debug features run on this clock |
| SAFETY_CHK | 0x0000000150 | 32 | rwNormal read/write | 0x00000000 | Safety endpoint connectivity check Register: Safety Requirement to provide a RW register that
will allow S/W to check the connectivity of a connection without impacting the functional path |
| RST_DBG | 0x0000000300 | 1 | rwNormal read/write | 0x00000001 | Reset for SOC Debug Logic |
| RST_PCIE_CONFIG | 0x0000000304 | 1 | rwNormal read/write | 0x00000001 | Reset for PCIe configuration Registers (PCIE_ATTRIB*) |
| RST_PCIE_CORE0 | 0x0000000308 | 1 | rwNormal read/write | 0x00000001 | Reset for PCIe core0 |
| RST_PCIE_CORE1 | 0x000000030C | 1 | rwNormal read/write | 0x00000001 | Reset for PCIe core1 |
| RST_CMN | 0x0000000314 | 1 | rwNormal read/write | 0x00000001 | Reset for CMN block |
| RST_L2_0 | 0x0000000318 | 1 | rwNormal read/write | 0x00000001 | Reset for L2 block (includes CHI RegSlice and interrupt synchronization) |
| RST_L2_1 | 0x000000031C | 1 | rwNormal read/write | 0x00000001 | Reset for L2 block (includes CHI RegSlice and interrupt synchronization) |
| RST_ADDR_REMAP | 0x0000000320 | 1 | rwNormal read/write | 0x00000001 | Reset for Address Remap block |
| RST_CPI0 | 0x0000000324 | 1 | rwNormal read/write | 0x00000001 | Reset for CPI0 |
| RST_CPI1 | 0x0000000328 | 1 | rwNormal read/write | 0x00000001 | Reset for CPI1 |