CPM4_DMA_ATTR Module

Versal Adaptive SoC Register Reference (AM012)

Document ID

AM012

Release Date

2023-08-29

Revision

1.3

CPM4_DMA_ATTR Module Description

Module Name	CPM4_DMA_ATTR Module
Modules of this Type	CPM4_DMA_ATTR
Base Address	0x00FCA70000 (CPM4_DMA_ATTR)
Description	CPM4 PCIe DMA Attributes

CPM4_DMA_ATTR Module Register Summary

Register Name	Address	Width	Type	Reset Value	Description
MISC_CTRL	0x0000000000	1	rwNormal read/write	0x00000000	MISC_CTRL
ISR	0x0000000010	32	wtcReadable, write a 1 to clear	0x00000000	APB Interrupt Status
IMR	0x0000000014	32	roRead-only	0x00000001	APB Interrupt Mask
IER	0x0000000018	32	woWrite-only	0x00000000	APB Interrupt Enable
IDR	0x000000001C	32	woWrite-only	0x00000000	APB Interrupt Disable
Data_Width	0x0000000030	32	rwNormal read/write	0x00000000	Width of datapath: 000: 64 bit 001: 128 bit 010: 256 bit 011: 512 bit others: reserved Note: This bit field must be set as equal to the CPM4_PCIE0_ATTR.AXISTEN_IF_WIDTH register.
Enable_Secure	0x0000000034	32	rwNormal read/write	0x00000000	Interconnect supports the security feature for the AXI-Lite destination: 0: AxProt[1] is ignored and all transactions reaches the destination 1: If AxProt[1]=0, then the transaction reach the destination. 1: If AxProt[1]=1, then the transaction does not reach the destination.
Mask_50	0x0000000038	32	rwNormal read/write	0x00000000	Address masking for different datapath widths. Note: This register must be set to match the data width defined by the Data_Width register: For 64 bit, set = 6h07 For 128 bit, set = 6h0F For 256 bit, set = 6h1F For 512 bit, set = 6h3F
Metering_Enable	0x000000003C	32	rwNormal read/write	0x00000000	Meter requests to RQ to avoid overflow of the Rx Fifo. If disabled, Finite Completion Credits, must be enabled in PCIe IP. 0 - Disable metering 1 - Enable metering
root_Port	0x0000000040	32	rwNormal read/write	0x00000000	0 - Endpoint mode 1 - Root port mode
MSI_Rx_Decode_En	0x0000000044	32	rwNormal read/write	0x00000000	0 - Not decode MSI Range 1 - Decode MSI Range
slv_Timeout_Err_Dis	0x0000000048	32	rwNormal read/write	0x00000000	0 - Report Completion Timeout as SLVERR 1 - Dont report Completion Timeout as SLVERR
PCIe_if_Parity_Check	0x000000004C	32	rwNormal read/write	0x00000000	Check parity from PCIe RC, CQ bus
PCIe_RQ_BME_Check_Dis	0x0000000050	32	rwNormal read/write	0x00000000	Disable RQ checking of bme/flr and generation of error response
Enable	0x0000000054	32	rwNormal read/write	0x00000000	0 - dma is disabled; will cancel requests rcvd on AXI-MM Slaves. 1 - dma is enabled
multq_max	0x0000000058	32	rwNormal read/write	0x00000000	Number of multq queues enabled
XDMA_IRQ	0x000000005C	32	rwNormal read/write	0x00000000	Use xdma user irq interface
Bypass_MSIx	0x0000000060	32	rwNormal read/write	0x00000000	Bypass PCIe Core msix outputs to fabric. Should be set only if DMA is disabled (bridge mode). If set, user logic can directly use PCIe Core msix interface
TRQ_Src_Dis	0x0000000064	32	rwNormal read/write	0x00000000	Force src bit on register bus to 0
IRQ_Gen_via_Reg	0x0000000068	32	rwNormal read/write	0x00000000	Use Bridge Register to generate Interrupts
RAM_Init_Dis	0x000000006C	32	rwNormal read/write	0x00000000	Disable any ram initialization in dma
Spare_0_L	0x0000000070	32	rwNormal read/write	0x00000000	Bits,Field,Recommended setting,Description [31:29],xdma_c2h_axi_wr_cache[2:0],3h0,XDMA only. Specifies the awcache[2:0] for C2H0 writebacks to AXI MM. Awcache[3] is defined in the attr_dma_0_h attribute register. [28:25],xdma_c2h_axi_wr_sec[3:0],4h0,XDMA only. Specifies the awprot for C2H[3:0] writebacks to AXI MM [24:21],xdma_h2c_axi_rd_cache[3:0],4h0,XDMA only. Specifies the arcache[3:0] for H2C3 writebacks to AXI MM. [20:17],xdma_h2c_axi_rd_cache[3:0],4h0,XDMA only. Specifies the arcache[3:0] for H2C2 writebacks to AXI MM. [16:13],xdma_h2c_axi_rd_cache[3:0],4h0,XDMA only. Specifies the arcache[3:0] for H2C1 writebacks to AXI MM. [12:9],xdma_h2c_axi_rd_cache[3:0],4h0,XDMA only. Specifies the arcache[3:0] for H2C0 writebacks to AXI MM. [8:5],xdma_h2c_axi_rd_sec[3:0],4h0,XDMA only. Specifies the arprot for H2C[3:0] writebacks to AXI MM. [4:0],Reserved,5h0,Reserved
Spare_0_H	0x0000000074	32	rwNormal read/write	0x00000000	Bits,Field,Recommended setting,Description [31:26],system_id[5:0],6h0,System ID csr. Value that will be read from the dma global system_id register if the system_id_ovr attribute bit is set. System ID csr[15:6] defined in next attr_dma_spare_1_l register. [25],Reserved,1h0,Reserved [24],pasid_en,1h0,Enable PASID for DMA [23:16],Reserved,8h0,Reserved [15],xdma_byp_eng_flr_done,Mode,QDMA set to 0x1. XDMA: set to 0x0. Ignores XDMA engines for flr_done. [14],Reserved,1h0,Reserved [13],mdma_sw_ctxt_clr_all,1b1,"QDMA only. If set, Clear the descriptor hardware context and credit context ctxt when the descriptor software context is cleared."[12:9],xdma_c2h_axi_wr_cache[3:0],4h0,XDMA only. Specifies the awcache[3:0] for C2H3 writebacks to AXI MM. [8:5],xdma_c2h_axi_wr_cache[3:0],4h0,XDMA only. Specifies the awcache[3:0] for C2H2 writebacks to AXI MM. [4:1],xdma_c2h_axi_wr_cache[3:0],4h0,XDMA only. Specifies the awcache[3:0] for C2H1 writebacks to AXI MM. [0],xdma_c2h_axi_wr_cache[3],1h0,XDMA only. Specifies the awcache[3] for C2H0 writebacks to AXI MM. Awcache[2:0] is defined in attr_dma_spare_0_l attribute register.
Spare_1_L	0x0000000078	32	rwNormal read/write	0x00000000	Bits,Field,Recommended setting,Description [31:21],brdg_slv_pasid_offset[10:0],11h0,Pasid index offset[10:0] for bridge slave requests. Pasid index offset [11] is defined in the attr_dma_1_h attribute register. [20],Reserved,1h0,Reserved [19],axis_h2c_ext_cmp_en,1h1,"QDMA set to 0x1. Use external signal to indicating h2c stream packet is complete, for the purpose of issueing writeback and interrupts."[18],Reserved,1h0,Reserved [17],dma_bar_ext_en,1h1,"Recommended setting: 1b1. If set, enable the DMA PCIe bar aperture to AXI MM."[16:12],tcp_timeout_exp[4:0],5h12,"Recommended setting: 5h12. Exponential timer for TRQ completion timeout 2^exp[4:0], 0 = disabled. "[11],brdg_slv_pasid_en,1h0,Enable PASID for the Bridge. [10],system_id_ovr,1h0,"If set, the system id register will show the value of the system_id attribute"[9:0],system_id[15:6],10h0,System ID csr. Value that will be read from the dma global system_id register if the system_id_ovr attribute bit is set. System ID csr[5:0] defined in attr_dma_0_h attribute register.
Spare_1_H	0x000000007C	32	rwNormal read/write	0x00000000	Bits,Field,Recommended setting,Description [31],xdma_drain_dat_en,1b1,XDMA set to 0x1. Enable draining of dat when run bit is not set for xdma. [30],xdma_drain_dsc_en,1b1,XDMA set to 0x1. Enable draining of dsc when run bit is not set for xdma. [29:28],Reserved,1h0,Reserved [27:16],brdg_slv_wr_pasid_offset[11:0],12h0,Pasid index offset for bridge slave write requests if shared_rdwr_pasid_dis is set [15],brdg_slv_shared_rdwr_pasid_dis,1h0,Enable different pasid for rd and writes from bridge slave. [14],Reserved,1h0,Reserved [13],axi_parity_chk_dis,1h0,Disable AXI slave parity checks [12:5],slv_fnc_msk[7:0],8h0,Mask for function bits received by aximm slave. Useful if number of functions supported needs less than 8 bits. Upper bits can then be used for SMID [4],Reserved,1h0,Reserved [3],fabric_reset_en,1b1,Enable reset from fabric [2],rrq_disable_en,1h0,Block new read requests on RQ timeout or register write [1],Reserved,1h0,Reserved [0],brdg_slv_pasid_offset[11],1h0,Pasid index offset[11] for bridge slave requests. Pasid index offset[10:0] is defined in the attr_dma_spare_1_l attribute register.
Spare_2_L	0x0000000080	32	rwNormal read/write	0x00000000	Bits,Field,Recommended setting,Description [31:21],misc_cap[10:0],11h0,"Used to advertise configured capabilities and version information to software. Accessible in DMA_GLBL2_MISC_CAP register. Bits [31:11] defined in attr_dma_spare_2_h attribute register. misc_cap[10:2]: Reserved 9h0 misc_cap[1]: FLR ENABLE misc_cap[0]: MAILBOX_ENABLE"[20],st_rx_msg_if_en,1b0," If set, send vdm to the streaming i/f"[19],exp_rom_bar_to_axil,1b0," If set, send hits to bar 6 (exp rom) to axi-lite"[18:15],Reserved,4h0,Reserved [14],trq_timeout_dat,1h0," If set, return all 1 for tcp timeout data, else all 0"[13],trq_timeout_rsp,1h0," If set, return all slv_err for tcp timeout response, else okay"[12:11],Reserved,2h0,Reserved [10],axi_slv_brdge_range,1h0," Specifies the size of the Bridge slave address aperture on AXI-MM. 1b1: 16M, 1b0: 256M"[9:0],Reserved,10h0,Reserved
Spare_2_H	0x0000000084	32	rwNormal read/write	0x00000000	Bits,Field,Recommended setting,Description [31:22],Reserved,10h0,Reserved [21],cfg_space_delay_en,1h0,"If set, enable Bridge register to control config space enable in the EP mode"[20:0],misc_cap[31:11],21h0,"Used to advertise configured capabilities and version information to software. Accessible in DMA_GLBL2_MISC_CAP register. Bits [10:0] defined in previous attribute register. misc_cap[31:16] RTL_VERSION misc_cap[15:11]: Reserved 5h0
Spare_3_L	0x0000000088	32	rwNormal read/write	0x00000000	Bits,Field,Recommended setting,Description [31:17],Reserved,15h0,Reserved [16:13],qinv_cnt_limit,4h1,"Affects QDMA only. If qinv_limit_en is set, this is the limit of qinv from dsc engine through c2h st pfch_evt_fifo that is allowed"[12],qinv_limit_en,4h1,"Affects QDMA only. If set, limit the number of qinvalidation in the pipe from dsc engine through C2H ST pfch_evt_fifo."[11],qinv_arb_stall,1h0,"Affects QDMA only. If set, allow descriptor fetching to continue even if tm_dsc_sts is full."[10],brdg_rro_en,1h0,"If set, enable relaxed ordering for all bridge slave reads to pcie."[9],Reserved,1h0,Reserved [8],pcie_mrs_reg_en,1h0,"If set, pcie max read size used will be defined by register"[7],pcie_mpl_reg_en,1h0,"If set, pcie max payload used will be define by register"[6:0],Reserved,7h0,Reserved
Spare_3_H	0x000000008C	32	rwNormal read/write	0x00000000	Bits,Field,Recommended setting,Description [31:0],Reserved,32h0,Reserved
PF_BarLite_Int	0x0000000090	32	rwNormal read/write	0x00000000	attr_dma_pf_barlite_int[5:0] represent the 6 32 bit bars for PF0. attr_dma_pf_barlite_int[11:6] represent the 6 32 bit bars for PF1. attr_dma_pf_barlite_int[17:12] represent the 6 32 bit bars for PF2. attr_dma_pf_barlite_int[23:18] represent the 6 32 bit bars for PF3. A value of 1 in the index position indicates that if a CQ request hits the corresponding physical bar for this PF, it will be routed to the DMA internal register space. For 64 bit bars only index 0, 2, 4 are valid since physical bar 1 and 0 are combined (index 0), 3 and 2 are combined (index 2), and 5 and 4 are combined (index 4).
PF_VF_BarLite_Int	0x0000000094	32	rwNormal read/write	0x00000000	Maps PF VF/barhit to DMA register space [23:18] = 1 bit per PF3 VF BAR indicating which BARs map to dma/bridge register space. [17:12] = 1 bit per PF2 VF BAR indicating which BARs map to dma/bridge register space. [11:6] = 1 bit per PF1 VF BAR indicating which BARs map to dma/bridge register space. [5:0] = 1 bit per PF0 VF BAR indicating which BARs map to dma/bridge register space.
PF_BarLite_Ext	0x0000000098	32	rwNormal read/write	0x00000000	Map PFs and barhit to axi-lite master. Everest hard ip does not have dedicated AXI-Lite master, so disabled with all 0.
PF_VF_BarLite_Ext	0x000000009C	32	rwNormal read/write	0x00000000	Map VFs and barhit to axi-lite master. Everest hard ip does not have dedicated AXI-Lite master, so disabled with all 0.
Cfg_Timeout_Err_Dis	0x00000000A0	32	rwNormal read/write	0x00000000	completion timeout error disable for CfgWr & CfgRd requests. In case of timeout error: If attr_dma_cfg_timeout_err_dis=1, the completion response is OK and data contains 0xFFFFFFFF. If 0, SLVERR response is returned.
Cfg_UR_Err_Dis	0x00000000A4	32	rwNormal read/write	0x00000000	UR error response disable for CfgRd requests. In case of PCIE core returns a UR response on RC interface: If attr_dma_cfg_ur_err_dis=1, it returns OK on axilite response and 0xFFFFFFF on data bus. If 0, DECERR response is returned.
Cfg_CRS_Sw_Visible_En	0x00000000A8	32	rwNormal read/write	0x00000000	CRS error response disable for CfgRd requests. In case of PCIE core returns a CRS response on RC interface: If attr_dma_cfg_crs_sw_visible_en=1, it returns OK on axilite response and 0xFFFF0001 on data bus. If 0, the request is sent to PCIE again (upto 256 times) to look for a successful response. If a 'CRS' response is still returned by the PCIE core, a 'DECERR' response is returned on the rresp bus.
AXI_slv_brdg_Base_Addr_L	0x00000000B0	32	rwNormal read/write	0x00000000	256MB space - base determined by PS. This is base address of ECAM where 0x00 to 0xE00 offsets would be the config space window, and VSCE capability starts from 0xE00 followed by bridge registers
AXI_slv_brdg_Base_Addr_H	0x00000000B4	32	rwNormal read/write	0x00000000	256MB space - base determined by PS. This is base address of ECAM where 0x00 to 0xE00 offsets would be the config space window, and VSCE capability starts from 0xE00 followed by bridge registers
AXI_slv_MultQ_Base_Addr_L	0x00000000B8	32	rwNormal read/write	0x00000000	16MB space (256 * 64K) - base dtermined by PS. This is the base address of the QDMA registers.
AXI_slv_MultQ_Base_Addr_H	0x00000000BC	32	rwNormal read/write	0x00000000	16MB space (256 * 64K) - base dtermined by PS. This is the base address of the QDMA registers
AXI_slv_XDMA_Base_Addr_L	0x00000000C0	32	rwNormal read/write	0x00000000	64K space - base determined by PS. This is the base address of the XDMA registers.
AXI_slv_XDMA_Base_Addr_H	0x00000000C4	32	rwNormal read/write	0x00000000	64K space - base determined by PS. This is the base address of the XDMA registers.
aximm_dma_steering_mode	0x00000000C8	32	rwNormal read/write	0x00000000	Steering mode to determine which MM Master Port DMA transactions will use. 0: mapped - channels will use attribute configured MM port 1: toggle - Requests will alternate between ports. This mechanism does not distinguish between channels.
aximm_dsc_Port	0x00000000CC	32	rwNormal read/write	0x00000000	Steering mode to determine which MM Master Port Descriptor Fetch transactions will use. 0: descriptor requests will be issued on MM0 1: descriptor requests will be issued on MM1
aximm_bridge_Port	0x00000000D0	32	rwNormal read/write	0x00000000	Steering mode to determine which MM Master Port Bridge transactions will use. 0: bridge requests will be issued on MM0 1: bridge requests will be issued on MM1
XDMA_PF	0x00000000DC	32	rwNormal read/write	0x00000000	Tie 0. Physical function of XDMA
mdma_Cfg_0_L	0x00000000E0	32	rwNormal read/write	0x00000000	Mdma configuration attributes
mdma_Cfg_0_H	0x00000000E4	32	rwNormal read/write	0x00000000	Mdma configuration attributes
mdma_Cfg_1_L	0x00000000E8	32	rwNormal read/write	0x00000000	Mdma configuration attributes
mdma_Cfg_1_H	0x00000000EC	32	rwNormal read/write	0x00000000	Mdma configuration attributes
mdma_Cfg_2_L	0x00000000F0	32	rwNormal read/write	0x00000000	Mdma configuration attributes
mdma_Cfg_2_H	0x00000000F4	32	rwNormal read/write	0x00000000	Mdma configuration attributes
mdma_Cfg_3_L	0x00000000F8	32	rwNormal read/write	0x00000000	Mdma configuration attributes
mdma_Cfg_3_H	0x00000000FC	32	rwNormal read/write	0x00000000	Mdma configuration attributes
PCIeBar_Num	0x0000000100	32	rwNormal read/write	0x00000000	Number of pcie bars enabled
AXIBar_Base_0_L	0x0000000104	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_0_H	0x0000000108	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_1_L	0x000000010C	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_1_H	0x0000000110	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_2_L	0x0000000114	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_2_H	0x0000000118	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_3_L	0x000000011C	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_3_H	0x0000000120	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_4_L	0x0000000124	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_4_H	0x0000000128	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_5_L	0x000000012C	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_Base_5_H	0x0000000130	32	rwNormal read/write	0x00000000	AXI to PCIe bar base
AXIBar_AS_0	0x0000000134	32	rwNormal read/write	0x00000000	32 or 64 bit address size
AXIBar_AS_1	0x0000000138	32	rwNormal read/write	0x00000000	32 or 64 bit address size
AXIBar_AS_2	0x000000013C	32	rwNormal read/write	0x00000000	32 or 64 bit address size
AXIBar_AS_3	0x0000000140	32	rwNormal read/write	0x00000000	32 or 64 bit address size
AXIBar_AS_4	0x0000000144	32	rwNormal read/write	0x00000000	32 or 64 bit address size
AXIBar_AS_5	0x0000000148	32	rwNormal read/write	0x00000000	32 or 64 bit address size
AXIBar_Attr_0	0x000000014C	32	rwNormal read/write	0x00000000	bar attributes [0]: relaxed read txn. base[0] and higaddr[0] for this bar must also be set
AXIBar_Attr_1	0x0000000150	32	rwNormal read/write	0x00000000	bar attributes [0]: relaxed read txn. base[0] and higaddr[0] for this bar must also be set
AXIBar_Attr_2	0x0000000154	32	rwNormal read/write	0x00000000	bar attributes [0]: relaxed read txn. base[0] and higaddr[0] for this bar must also be set
AXIBar_Attr_3	0x0000000158	32	rwNormal read/write	0x00000000	bar attributes [0]: relaxed read txn. base[0] and higaddr[0] for this bar must also be set
AXIBar_Attr_4	0x000000015C	32	rwNormal read/write	0x00000000	bar attributes [0]: relaxed read txn. base[0] and higaddr[0] for this bar must also be set
AXIBar_Attr_5	0x0000000160	32	rwNormal read/write	0x00000000	bar attributes [0]: relaxed read txn. base[0] and higaddr[0] for this bar must also be set
AXIBar_Highaddr_0_L	0x0000000164	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_0_H	0x0000000168	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_1_L	0x000000016C	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_1_H	0x0000000170	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_2_L	0x0000000174	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_2_H	0x0000000178	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_3_L	0x000000017C	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_3_H	0x0000000180	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_4_L	0x0000000184	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_4_H	0x0000000188	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_5_L	0x000000018C	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar_Highaddr_5_H	0x0000000190	32	rwNormal read/write	0x00000000	AXI to PCIe bar high address
AXIBar2PCIeBar_0_L	0x0000000194	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_0_H	0x0000000198	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_1_L	0x000000019C	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_1_H	0x00000001A0	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_2_L	0x00000001A4	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_2_H	0x00000001A8	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_3_L	0x00000001AC	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_3_H	0x00000001B0	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_4_L	0x00000001B4	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_4_H	0x00000001B8	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_5_L	0x00000001BC	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_5_H	0x00000001C0	32	rwNormal read/write	0x00000000	AXI to PCIe bar translation
AXIBar2PCIeBar_Sec_0	0x00000001C4	32	rwNormal read/write	0x00000000	AXI to PCIe bar security
AXIBar2PCIeBar_Sec_1	0x00000001C8	32	rwNormal read/write	0x00000000	AXI to PCIe bar security
AXIBar2PCIeBar_Sec_2	0x00000001CC	32	rwNormal read/write	0x00000000	AXI to PCIe bar security
AXIBar2PCIeBar_Sec_3	0x00000001D0	32	rwNormal read/write	0x00000000	AXI to PCIe bar security
AXIBar2PCIeBar_Sec_4	0x00000001D4	32	rwNormal read/write	0x00000000	AXI to PCIe bar security
AXIBar2PCIeBar_Sec_5	0x00000001D8	32	rwNormal read/write	0x00000000	AXI to PCIe bar security
PCIeBar2AXIBar_0_PF0_L	0x00000001DC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR0
PCIeBar2AXIBar_0_PF0_H	0x00000001E0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR0
PCIeBar2AXIBar_1_PF0_L	0x00000001E4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR1
PCIeBar2AXIBar_1_PF0_H	0x00000001E8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR1
PCIeBar2AXIBar_2_PF0_L	0x00000001EC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR2
PCIeBar2AXIBar_2_PF0_H	0x00000001F0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR2
PCIeBar2AXIBar_3_PF0_L	0x00000001F4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR3
PCIeBar2AXIBar_3_PF0_H	0x00000001F8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR3
PCIeBar2AXIBar_4_PF0_L	0x00000001FC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0BAR4
PCIeBar2AXIBar_4_PF0_H	0x0000000200	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0BAR4
PCIeBar2AXIBar_5_PF0_L	0x0000000204	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR5
PCIeBar2AXIBar_5_PF0_H	0x0000000208	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 BAR5
PCIeBar2AXIBar_6_PF0_L	0x000000020C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 EXP BAR
PCIeBar2AXIBar_6_PF0_H	0x0000000210	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 EXP BAR
PCIeBar2AXIBar_0_Rd_Sec_PF0	0x0000000214	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR0 reads
PCIeBar2AXIBar_1_Rd_Sec_PF0	0x0000000218	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR1 reads
PCIeBar2AXIBar_2_Rd_Sec_PF0	0x000000021C	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR2 reads
PCIeBar2AXIBar_3_Rd_Sec_PF0	0x0000000220	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR3 reads
PCIeBar2AXIBar_4_Rd_Sec_PF0	0x0000000224	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR4 reads
PCIeBar2AXIBar_5_Rd_Sec_PF0	0x0000000228	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR5 reads
PCIeBar2AXIBar_6_Rd_Sec_PF0	0x000000022C	32	rwNormal read/write	0x00000000	ARPROT value for PF0 EXP BAR reads
PCIeBar2AXIBar_0_Rd_Cache_PF0	0x0000000230	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR0 reads
PCIeBar2AXIBar_1_Rd_Cache_PF0	0x0000000234	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR1 reads
PCIeBar2AXIBar_2_Rd_Cache_PF0	0x0000000238	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR2 reads
PCIeBar2AXIBar_3_Rd_Cache_PF0	0x000000023C	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR3 reads
PCIeBar2AXIBar_4_Rd_Cache_PF0	0x0000000240	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR4 reads
PCIeBar2AXIBar_5_Rd_Cache_PF0	0x0000000244	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR5 reads
PCIeBar2AXIBar_6_Rd_Cache_PF0	0x0000000248	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 EXP BAR reads
PCIeBar2AXIBar_0_Wr_Sec_PF0	0x000000024C	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR0 writes
PCIeBar2AXIBar_1_Wr_Sec_PF0	0x0000000250	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR1 writes
PCIeBar2AXIBar_2_Wr_Sec_PF0	0x0000000254	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR2 writes
PCIeBar2AXIBar_3_Wr_Sec_PF0	0x0000000258	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR3 writes
PCIeBar2AXIBar_4_Wr_Sec_PF0	0x000000025C	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR4 writes
PCIeBar2AXIBar_5_Wr_Sec_PF0	0x0000000260	32	rwNormal read/write	0x00000000	ARPROT value for PF0 BAR5 writes
PCIeBar2AXIBar_6_Wr_Sec_PF0	0x0000000264	32	rwNormal read/write	0x00000000	ARPROT value for PF0 EXP BAR writes
PCIeBar2AXIBar_0_Wr_Cache_PF0	0x0000000268	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR0 writes
PCIeBar2AXIBar_1_Wr_Cache_PF0	0x000000026C	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR1 writes
PCIeBar2AXIBar_2_Wr_Cache_PF0	0x0000000270	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR2 writes
PCIeBar2AXIBar_3_Wr_Cache_PF0	0x0000000274	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR3 writes
PCIeBar2AXIBar_4_Wr_Cache_PF0	0x0000000278	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR4 writes
PCIeBar2AXIBar_5_Wr_Cache_PF0	0x000000027C	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 BAR5 writes
PCIeBar2AXIBar_6_Wr_Cache_PF0	0x0000000280	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 EXP BAR writes
PCIeBar2AXIBar_0_Len_PF0	0x0000000284	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 BAR0
PCIeBar2AXIBar_1_Len_PF0	0x0000000288	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 BAR1
PCIeBar2AXIBar_2_Len_PF0	0x000000028C	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 BAR2
PCIeBar2AXIBar_3_Len_PF0	0x0000000290	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 BAR3
PCIeBar2AXIBar_4_Len_PF0	0x0000000294	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 BAR4
PCIeBar2AXIBar_5_Len_PF0	0x0000000298	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 BAR5
PCIeBar2AXIBar_6_Len_PF0	0x000000029C	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 EXP BAR
PCIeBar2AXIBar_0_PF1_L	0x00000002A0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR0
PCIeBar2AXIBar_0_PF1_H	0x00000002A4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR0
PCIeBar2AXIBar_1_PF1_L	0x00000002A8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR1
PCIeBar2AXIBar_1_PF1_H	0x00000002AC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR1
PCIeBar2AXIBar_2_PF1_L	0x00000002B0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR2
PCIeBar2AXIBar_2_PF1_H	0x00000002B4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR2
PCIeBar2AXIBar_3_PF1_L	0x00000002B8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR3
PCIeBar2AXIBar_3_PF1_H	0x00000002BC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR3
PCIeBar2AXIBar_4_PF1_L	0x00000002C0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1BAR4
PCIeBar2AXIBar_4_PF1_H	0x00000002C4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1BAR4
PCIeBar2AXIBar_5_PF1_L	0x00000002C8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR5
PCIeBar2AXIBar_5_PF1_H	0x00000002CC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 BAR5
PCIeBar2AXIBar_6_PF1_L	0x00000002D0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 EXP BAR
PCIeBar2AXIBar_6_PF1_H	0x00000002D4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 EXP BAR
PCIeBar2AXIBar_0_Rd_Sec_PF1	0x00000002D8	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR0 reads
PCIeBar2AXIBar_1_Rd_Sec_PF1	0x00000002DC	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR1 reads
PCIeBar2AXIBar_2_Rd_Sec_PF1	0x00000002E0	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR2 reads
PCIeBar2AXIBar_3_Rd_Sec_PF1	0x00000002E4	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR3 reads
PCIeBar2AXIBar_4_Rd_Sec_PF1	0x00000002E8	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR4 reads
PCIeBar2AXIBar_5_Rd_Sec_PF1	0x00000002EC	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR5 reads
PCIeBar2AXIBar_6_Rd_Sec_PF1	0x00000002F0	32	rwNormal read/write	0x00000000	ARPROT value for PF1 EXP BAR reads
PCIeBar2AXIBar_0_Rd_Cache_PF1	0x00000002F4	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR0 reads
PCIeBar2AXIBar_1_Rd_Cache_PF1	0x00000002F8	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR1 reads
PCIeBar2AXIBar_2_Rd_Cache_PF1	0x00000002FC	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR2 reads
PCIeBar2AXIBar_3_Rd_Cache_PF1	0x0000000300	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR3 reads
PCIeBar2AXIBar_4_Rd_Cache_PF1	0x0000000304	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR4 reads
PCIeBar2AXIBar_5_Rd_Cache_PF1	0x0000000308	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR5 reads
PCIeBar2AXIBar_6_Rd_Cache_PF1	0x000000030C	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 EXP BAR reads
PCIeBar2AXIBar_0_Wr_Sec_PF1	0x0000000310	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR0 writes
PCIeBar2AXIBar_1_Wr_Sec_PF1	0x0000000314	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR1 writes
PCIeBar2AXIBar_2_Wr_Sec_PF1	0x0000000318	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR2 writes
PCIeBar2AXIBar_3_Wr_Sec_PF1	0x000000031C	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR3 writes
PCIeBar2AXIBar_4_Wr_Sec_PF1	0x0000000320	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR4 writes
PCIeBar2AXIBar_5_Wr_Sec_PF1	0x0000000324	32	rwNormal read/write	0x00000000	ARPROT value for PF1 BAR5 writes
PCIeBar2AXIBar_6_Wr_Sec_PF1	0x0000000328	32	rwNormal read/write	0x00000000	ARPROT value for PF1 EXP BAR writes
PCIeBar2AXIBar_0_Wr_Cache_PF1	0x000000032C	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR0 writes
PCIeBar2AXIBar_1_Wr_Cache_PF1	0x0000000330	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR1 writes
PCIeBar2AXIBar_2_Wr_Cache_PF1	0x0000000334	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR2 writes
PCIeBar2AXIBar_3_Wr_Cache_PF1	0x0000000338	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR3 writes
PCIeBar2AXIBar_4_Wr_Cache_PF1	0x000000033C	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR4 writes
PCIeBar2AXIBar_5_Wr_Cache_PF1	0x0000000340	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 BAR5 writes
PCIeBar2AXIBar_6_Wr_Cache_PF1	0x0000000344	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 EXP BAR writes
PCIeBar2AXIBar_0_Len_PF1	0x0000000348	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 BAR0
PCIeBar2AXIBar_1_Len_PF1	0x000000034C	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 BAR1
PCIeBar2AXIBar_2_Len_PF1	0x0000000350	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 BAR2
PCIeBar2AXIBar_3_Len_PF1	0x0000000354	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 BAR3
PCIeBar2AXIBar_4_Len_PF1	0x0000000358	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 BAR4
PCIeBar2AXIBar_5_Len_PF1	0x000000035C	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 BAR5
PCIeBar2AXIBar_6_Len_PF1	0x0000000360	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 EXP BAR
PCIeBar2AXIBar_0_PF2_L	0x0000000364	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR0
PCIeBar2AXIBar_0_PF2_H	0x0000000368	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR0
PCIeBar2AXIBar_1_PF2_L	0x000000036C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR1
PCIeBar2AXIBar_1_PF2_H	0x0000000370	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR1
PCIeBar2AXIBar_2_PF2_L	0x0000000374	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR2
PCIeBar2AXIBar_2_PF2_H	0x0000000378	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR2
PCIeBar2AXIBar_3_PF2_L	0x000000037C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR3
PCIeBar2AXIBar_3_PF2_H	0x0000000380	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR3
PCIeBar2AXIBar_4_PF2_L	0x0000000384	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2BAR4
PCIeBar2AXIBar_4_PF2_H	0x0000000388	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2BAR4
PCIeBar2AXIBar_5_PF2_L	0x000000038C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR5
PCIeBar2AXIBar_5_PF2_H	0x0000000390	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 BAR5
PCIeBar2AXIBar_6_PF2_L	0x0000000394	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 EXP BAR
PCIeBar2AXIBar_6_PF2_H	0x0000000398	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 EXP BAR
PCIeBar2AXIBar_0_Rd_Sec_PF2	0x000000039C	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR0 reads
PCIeBar2AXIBar_1_Rd_Sec_PF2	0x00000003A0	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR1 reads
PCIeBar2AXIBar_2_Rd_Sec_PF2	0x00000003A4	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR2 reads
PCIeBar2AXIBar_3_Rd_Sec_PF2	0x00000003A8	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR3 reads
PCIeBar2AXIBar_4_Rd_Sec_PF2	0x00000003AC	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR4 reads
PCIeBar2AXIBar_5_Rd_Sec_PF2	0x00000003B0	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR5 reads
PCIeBar2AXIBar_6_Rd_Sec_PF2	0x00000003B4	32	rwNormal read/write	0x00000000	ARPROT value for PF2 EXP BAR reads
PCIeBar2AXIBar_0_Rd_Cache_PF2	0x00000003B8	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR0 reads
PCIeBar2AXIBar_1_Rd_Cache_PF2	0x00000003BC	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR1 reads
PCIeBar2AXIBar_2_Rd_Cache_PF2	0x00000003C0	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR2 reads
PCIeBar2AXIBar_3_Rd_Cache_PF2	0x00000003C4	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR3 reads
PCIeBar2AXIBar_4_Rd_Cache_PF2	0x00000003C8	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR4 reads
PCIeBar2AXIBar_5_Rd_Cache_PF2	0x00000003CC	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR5 reads
PCIeBar2AXIBar_6_Rd_Cache_PF2	0x00000003D0	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 EXP BAR reads
PCIeBar2AXIBar_0_Wr_Sec_PF2	0x00000003D4	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR0 writes
PCIeBar2AXIBar_1_Wr_Sec_PF2	0x00000003D8	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR1 writes
PCIeBar2AXIBar_2_Wr_Sec_PF2	0x00000003DC	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR2 writes
PCIeBar2AXIBar_3_Wr_Sec_PF2	0x00000003E0	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR3 writes
PCIeBar2AXIBar_4_Wr_Sec_PF2	0x00000003E4	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR4 writes
PCIeBar2AXIBar_5_Wr_Sec_PF2	0x00000003E8	32	rwNormal read/write	0x00000000	ARPROT value for PF2 BAR5 writes
PCIeBar2AXIBar_6_Wr_Sec_PF2	0x00000003EC	32	rwNormal read/write	0x00000000	ARPROT value for PF2 EXP BAR writes
PCIeBar2AXIBar_0_Wr_Cache_PF2	0x00000003F0	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR0 writes
PCIeBar2AXIBar_1_Wr_Cache_PF2	0x00000003F4	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR1 writes
PCIeBar2AXIBar_2_Wr_Cache_PF2	0x00000003F8	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR2 writes
PCIeBar2AXIBar_3_Wr_Cache_PF2	0x00000003FC	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR3 writes
PCIeBar2AXIBar_4_Wr_Cache_PF2	0x0000000400	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR4 writes
PCIeBar2AXIBar_5_Wr_Cache_PF2	0x0000000404	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 BAR5 writes
PCIeBar2AXIBar_6_Wr_Cache_PF2	0x0000000408	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 EXP BAR writes
PCIeBar2AXIBar_0_Len_PF2	0x000000040C	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 BAR0
PCIeBar2AXIBar_1_Len_PF2	0x0000000410	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 BAR1
PCIeBar2AXIBar_2_Len_PF2	0x0000000414	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 BAR2
PCIeBar2AXIBar_3_Len_PF2	0x0000000418	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 BAR3
PCIeBar2AXIBar_4_Len_PF2	0x000000041C	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 BAR4
PCIeBar2AXIBar_5_Len_PF2	0x0000000420	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 BAR5
PCIeBar2AXIBar_6_Len_PF2	0x0000000424	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 EXP BAR
PCIeBar2AXIBar_0_PF3_L	0x0000000428	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR0
PCIeBar2AXIBar_0_PF3_H	0x000000042C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR0
PCIeBar2AXIBar_1_PF3_L	0x0000000430	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR1
PCIeBar2AXIBar_1_PF3_H	0x0000000434	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR1
PCIeBar2AXIBar_2_PF3_L	0x0000000438	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR2
PCIeBar2AXIBar_2_PF3_H	0x000000043C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR2
PCIeBar2AXIBar_3_PF3_L	0x0000000440	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR3
PCIeBar2AXIBar_3_PF3_H	0x0000000444	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR3
PCIeBar2AXIBar_4_PF3_L	0x0000000448	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3BAR4
PCIeBar2AXIBar_4_PF3_H	0x000000044C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3BAR4
PCIeBar2AXIBar_5_PF3_L	0x0000000450	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR5
PCIeBar2AXIBar_5_PF3_H	0x0000000454	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 BAR5
PCIeBar2AXIBar_6_PF3_L	0x0000000458	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 EXP BAR
PCIeBar2AXIBar_6_PF3_H	0x000000045C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 EXP BAR
PCIeBar2AXIBar_0_Rd_Sec_PF3	0x0000000460	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR0 reads
PCIeBar2AXIBar_1_Rd_Sec_PF3	0x0000000464	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR1 reads
PCIeBar2AXIBar_2_Rd_Sec_PF3	0x0000000468	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR2 reads
PCIeBar2AXIBar_3_Rd_Sec_PF3	0x000000046C	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR3 reads
PCIeBar2AXIBar_4_Rd_Sec_PF3	0x0000000470	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR4 reads
PCIeBar2AXIBar_5_Rd_Sec_PF3	0x0000000474	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR5 reads
PCIeBar2AXIBar_6_Rd_Sec_PF3	0x0000000478	32	rwNormal read/write	0x00000000	ARPROT value for PF3 EXP ROM reads
PCIeBar2AXIBar_0_Rd_Cache_PF3	0x000000047C	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR0 reads
PCIeBar2AXIBar_1_Rd_Cache_PF3	0x0000000480	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR1 reads
PCIeBar2AXIBar_2_Rd_Cache_PF3	0x0000000484	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR2 reads
PCIeBar2AXIBar_3_Rd_Cache_PF3	0x0000000488	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR3 reads
PCIeBar2AXIBar_4_Rd_Cache_PF3	0x000000048C	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR4 reads
PCIeBar2AXIBar_5_Rd_Cache_PF3	0x0000000490	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR5 reads
PCIeBar2AXIBar_6_Rd_Cache_PF3	0x0000000494	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 EXP BAR reads
PCIeBar2AXIBar_0_Wr_Sec_PF3	0x0000000498	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR0 writes
PCIeBar2AXIBar_1_Wr_Sec_PF3	0x000000049C	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR1 writes
PCIeBar2AXIBar_2_Wr_Sec_PF3	0x00000004A0	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR2 writes
PCIeBar2AXIBar_3_Wr_Sec_PF3	0x00000004A4	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR3 writes
PCIeBar2AXIBar_4_Wr_Sec_PF3	0x00000004A8	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR4 writes
PCIeBar2AXIBar_5_Wr_Sec_PF3	0x00000004AC	32	rwNormal read/write	0x00000000	ARPROT value for PF3 BAR5 writes
PCIeBar2AXIBar_6_Wr_Sec_PF3	0x00000004B0	32	rwNormal read/write	0x00000000	ARPROT value for PF3 EXP BAR writes
PCIeBar2AXIBar_0_Wr_Cache_PF3	0x00000004B4	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR0 writes
PCIeBar2AXIBar_1_Wr_Cache_PF3	0x00000004B8	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR1 writes
PCIeBar2AXIBar_2_Wr_Cache_PF3	0x00000004BC	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR2 writes
PCIeBar2AXIBar_3_Wr_Cache_PF3	0x00000004C0	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR3 writes
PCIeBar2AXIBar_4_Wr_Cache_PF3	0x00000004C4	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR4 writes
PCIeBar2AXIBar_5_Wr_Cache_PF3	0x00000004C8	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 BAR5 writes
PCIeBar2AXIBar_6_Wr_Cache_PF3	0x00000004CC	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 EXP BAR writes
PCIeBar2AXIBar_0_Len_PF3	0x00000004D0	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 BAR0
PCIeBar2AXIBar_1_Len_PF3	0x00000004D4	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 BAR1
PCIeBar2AXIBar_2_Len_PF3	0x00000004D8	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 BAR2
PCIeBar2AXIBar_3_Len_PF3	0x00000004DC	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 BAR3
PCIeBar2AXIBar_4_Len_PF3	0x00000004E0	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 BAR4
PCIeBar2AXIBar_5_Len_PF3	0x00000004E4	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 BAR5
PCIeBar2AXIBar_6_Len_PF3	0x00000004E8	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 EXP BAR
PCIeBar2AXIBar_0_bar_PF0_VF_L	0x00000004EC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR0
PCIeBar2AXIBar_0_bar_PF0_VF_H	0x00000004F0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR0
PCIeBar2AXIBar_1_bar_PF0_VF_L	0x00000004F4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR1
PCIeBar2AXIBar_1_bar_PF0_VF_H	0x00000004F8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR1
PCIeBar2AXIBar_2_bar_PF0_VF_L	0x00000004FC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR2
PCIeBar2AXIBar_2_bar_PF0_VF_H	0x0000000500	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR2
PCIeBar2AXIBar_3_bar_PF0_VF_L	0x0000000504	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR3
PCIeBar2AXIBar_3_bar_PF0_VF_H	0x0000000508	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR3
PCIeBar2AXIBar_4_bar_PF0_VF_L	0x000000050C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VFBAR4
PCIeBar2AXIBar_4_bar_PF0_VF_H	0x0000000510	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VFBAR4
PCIeBar2AXIBar_5_bar_PF0_VF_L	0x0000000514	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR5
PCIeBar2AXIBar_5_bar_PF0_VF_H	0x0000000518	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR5
PCIeBar2AXIBar_6_bar_PF0_VF_L	0x000000051C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR6
PCIeBar2AXIBar_6_bar_PF0_VF_H	0x0000000520	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF0 VF BAR6
PCIeBar2AXIBar_0_Rd_Sec_PF0_VF	0x0000000524	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR0 reads
PCIeBar2AXIBar_1_Rd_Sec_PF0_VF	0x0000000528	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR1 reads
PCIeBar2AXIBar_2_Rd_Sec_PF0_VF	0x000000052C	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR2 reads
PCIeBar2AXIBar_3_Rd_Sec_PF0_VF	0x0000000530	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR3 reads
PCIeBar2AXIBar_4_Rd_Sec_PF0_VF	0x0000000534	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR4 reads
PCIeBar2AXIBar_5_Rd_Sec_PF0_VF	0x0000000538	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR5 reads
PCIeBar2AXIBar_6_Rd_Sec_PF0_VF	0x000000053C	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR6 reads
PCIeBar2AXIBar_0_Rd_Cache_PF0_VF	0x0000000540	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR0 reads
PCIeBar2AXIBar_1_Rd_Cache_PF0_VF	0x0000000544	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR1 reads
PCIeBar2AXIBar_2_Rd_Cache_PF0_VF	0x0000000548	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR2 reads
PCIeBar2AXIBar_3_Rd_Cache_PF0_VF	0x000000054C	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR3 reads
PCIeBar2AXIBar_4_Rd_Cache_PF0_VF	0x0000000550	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR4 reads
PCIeBar2AXIBar_5_Rd_Cache_PF0_VF	0x0000000554	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR5 reads
PCIeBar2AXIBar_6_Rd_Cache_PF0_VF	0x0000000558	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR6 reads
PCIeBar2AXIBar_0_Wr_Sec_PF0_VF	0x000000055C	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR0 writes
PCIeBar2AXIBar_1_Wr_Sec_PF0_VF	0x0000000560	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR1 writes
PCIeBar2AXIBar_2_Wr_Sec_PF0_VF	0x0000000564	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR2 writes
PCIeBar2AXIBar_3_Wr_Sec_PF0_VF	0x0000000568	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR3 writes
PCIeBar2AXIBar_4_Wr_Sec_PF0_VF	0x000000056C	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR4 writes
PCIeBar2AXIBar_5_Wr_Sec_PF0_VF	0x0000000570	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR5 writes
PCIeBar2AXIBar_6_Wr_Sec_PF0_VF	0x0000000574	32	rwNormal read/write	0x00000000	ARPROT value for PF0 VF BAR6 writes
PCIeBar2AXIBar_0_Wr_Cache_PF0_VF	0x0000000578	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR0 writes
PCIeBar2AXIBar_1_Wr_Cache_PF0_VF	0x000000057C	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR1 writes
PCIeBar2AXIBar_2_Wr_Cache_PF0_VF	0x0000000580	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR2 writes
PCIeBar2AXIBar_3_Wr_Cache_PF0_VF	0x0000000584	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR3 writes
PCIeBar2AXIBar_4_Wr_Cache_PF0_VF	0x0000000588	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR4 writes
PCIeBar2AXIBar_5_Wr_Cache_PF0_VF	0x000000058C	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR5 writes
PCIeBar2AXIBar_6_Wr_Cache_PF0_VF	0x0000000590	32	rwNormal read/write	0x00000000	ARCACHE value for PF0 VF BAR6 writes
PCIeBar2AXIBar_0_Len_PF0_VF	0x0000000594	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 VF BAR0
PCIeBar2AXIBar_1_Len_PF0_VF	0x0000000598	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 VF BAR1
PCIeBar2AXIBar_2_Len_PF0_VF	0x000000059C	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 VF BAR2
PCIeBar2AXIBar_3_Len_PF0_VF	0x00000005A0	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 VF BAR3
PCIeBar2AXIBar_4_Len_PF0_VF	0x00000005A4	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 VF BAR4
PCIeBar2AXIBar_5_Len_PF0_VF	0x00000005A8	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 VF BAR5
PCIeBar2AXIBar_6_Len_PF0_VF	0x00000005AC	32	rwNormal read/write	0x00000000	Bar size in bits for PF0 VF BAR6
PCIeBar2AXIBar_0_bar_PF1_VF_L	0x00000005B0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR0
PCIeBar2AXIBar_0_bar_PF1_VF_H	0x00000005B4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR0
PCIeBar2AXIBar_1_bar_PF1_VF_L	0x00000005B8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR1
PCIeBar2AXIBar_1_bar_PF1_VF_H	0x00000005BC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR1
PCIeBar2AXIBar_2_bar_PF1_VF_L	0x00000005C0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR2
PCIeBar2AXIBar_2_bar_PF1_VF_H	0x00000005C4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR2
PCIeBar2AXIBar_3_bar_PF1_VF_L	0x00000005C8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR3
PCIeBar2AXIBar_3_bar_PF1_VF_H	0x00000005CC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR3
PCIeBar2AXIBar_4_bar_PF1_VF_L	0x00000005D0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VFBAR4
PCIeBar2AXIBar_4_bar_PF1_VF_H	0x00000005D4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VFBAR4
PCIeBar2AXIBar_5_bar_PF1_VF_L	0x00000005D8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR5
PCIeBar2AXIBar_5_bar_PF1_VF_H	0x00000005DC	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR5
PCIeBar2AXIBar_6_bar_PF1_VF_L	0x00000005E0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR6
PCIeBar2AXIBar_6_bar_PF1_VF_H	0x00000005E4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF1 VF BAR6
PCIeBar2AXIBar_0_Rd_Sec_PF1_VF	0x00000005E8	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR0 reads
PCIeBar2AXIBar_1_Rd_Sec_PF1_VF	0x00000005EC	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR1 reads
PCIeBar2AXIBar_2_Rd_Sec_PF1_VF	0x00000005F0	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR2 reads
PCIeBar2AXIBar_3_Rd_Sec_PF1_VF	0x00000005F4	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR3 reads
PCIeBar2AXIBar_4_Rd_Sec_PF1_VF	0x00000005F8	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR4 reads
PCIeBar2AXIBar_5_Rd_Sec_PF1_VF	0x00000005FC	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR5 reads
PCIeBar2AXIBar_6_Rd_Sec_PF1_VF	0x0000000600	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR6 reads
PCIeBar2AXIBar_0_Rd_Cache_PF1_VF	0x0000000604	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR0 reads
PCIeBar2AXIBar_1_Rd_Cache_PF1_VF	0x0000000608	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR1 reads
PCIeBar2AXIBar_2_Rd_Cache_PF1_VF	0x000000060C	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR2 reads
PCIeBar2AXIBar_3_Rd_Cache_PF1_VF	0x0000000610	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR3 reads
PCIeBar2AXIBar_4_Rd_Cache_PF1_VF	0x0000000614	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR4 reads
PCIeBar2AXIBar_5_Rd_Cache_PF1_VF	0x0000000618	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR5 reads
PCIeBar2AXIBar_6_Rd_Cache_PF1_VF	0x000000061C	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR6 reads
PCIeBar2AXIBar_0_Wr_Sec_PF1_VF	0x0000000620	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR0 writes
PCIeBar2AXIBar_1_Wr_Sec_PF1_VF	0x0000000624	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR1 writes
PCIeBar2AXIBar_2_Wr_Sec_PF1_VF	0x0000000628	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR2 writes
PCIeBar2AXIBar_3_Wr_Sec_PF1_VF	0x000000062C	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR3 writes
PCIeBar2AXIBar_4_Wr_Sec_PF1_VF	0x0000000630	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR4 writes
PCIeBar2AXIBar_5_Wr_Sec_PF1_VF	0x0000000634	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR5 writes
PCIeBar2AXIBar_6_Wr_Sec_PF1_VF	0x0000000638	32	rwNormal read/write	0x00000000	ARPROT value for PF1 VF BAR6 writes
PCIeBar2AXIBar_0_Wr_Cache_PF1_VF	0x000000063C	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR0 writes
PCIeBar2AXIBar_1_Wr_Cache_PF1_VF	0x0000000640	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR1 writes
PCIeBar2AXIBar_2_Wr_Cache_PF1_VF	0x0000000644	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR2 writes
PCIeBar2AXIBar_3_Wr_Cache_PF1_VF	0x0000000648	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR3 writes
PCIeBar2AXIBar_4_Wr_Cache_PF1_VF	0x000000064C	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR4 writes
PCIeBar2AXIBar_5_Wr_Cache_PF1_VF	0x0000000650	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR5 writes
PCIeBar2AXIBar_6_Wr_Cache_PF1_VF	0x0000000654	32	rwNormal read/write	0x00000000	ARCACHE value for PF1 VF BAR6 writes
PCIeBar2AXIBar_0_Len_PF1_VF	0x0000000658	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 VF BAR0
PCIeBar2AXIBar_1_Len_PF1_VF	0x000000065C	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 VF BAR1
PCIeBar2AXIBar_2_Len_PF1_VF	0x0000000660	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 VF BAR2
PCIeBar2AXIBar_3_Len_PF1_VF	0x0000000664	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 VF BAR3
PCIeBar2AXIBar_4_Len_PF1_VF	0x0000000668	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 VF BAR4
PCIeBar2AXIBar_5_Len_PF1_VF	0x000000066C	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 VF BAR5
PCIeBar2AXIBar_6_Len_PF1_VF	0x0000000670	32	rwNormal read/write	0x00000000	Bar size in bits for PF1 VF BAR6
PCIeBar2AXIBar_0_bar_PF2_VF_L	0x0000000674	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR0
PCIeBar2AXIBar_0_bar_PF2_VF_H	0x0000000678	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR0
PCIeBar2AXIBar_1_bar_PF2_VF_L	0x000000067C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR1
PCIeBar2AXIBar_1_bar_PF2_VF_H	0x0000000680	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR1
PCIeBar2AXIBar_2_bar_PF2_VF_L	0x0000000684	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR2
PCIeBar2AXIBar_2_bar_PF2_VF_H	0x0000000688	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR2
PCIeBar2AXIBar_3_bar_PF2_VF_L	0x000000068C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR3
PCIeBar2AXIBar_3_bar_PF2_VF_H	0x0000000690	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR3
PCIeBar2AXIBar_4_bar_PF2_VF_L	0x0000000694	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VFBAR4
PCIeBar2AXIBar_4_bar_PF2_VF_H	0x0000000698	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VFBAR4
PCIeBar2AXIBar_5_bar_PF2_VF_L	0x000000069C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR5
PCIeBar2AXIBar_5_bar_PF2_VF_H	0x00000006A0	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR5
PCIeBar2AXIBar_6_bar_PF2_VF_L	0x00000006A4	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR6
PCIeBar2AXIBar_6_bar_PF2_VF_H	0x00000006A8	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF2 VF BAR6
PCIeBar2AXIBar_0_Rd_Sec_PF2_VF	0x00000006AC	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR0 reads
PCIeBar2AXIBar_1_Rd_Sec_PF2_VF	0x00000006B0	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR1 reads
PCIeBar2AXIBar_2_Rd_Sec_PF2_VF	0x00000006B4	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR2 reads
PCIeBar2AXIBar_3_Rd_Sec_PF2_VF	0x00000006B8	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR3 reads
PCIeBar2AXIBar_4_Rd_Sec_PF2_VF	0x00000006BC	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR4 reads
PCIeBar2AXIBar_5_Rd_Sec_PF2_VF	0x00000006C0	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR5 reads
PCIeBar2AXIBar_6_Rd_Sec_PF2_VF	0x00000006C4	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR6 reads
PCIeBar2AXIBar_0_Rd_Cache_PF2_VF	0x00000006C8	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR0 reads
PCIeBar2AXIBar_1_Rd_Cache_PF2_VF	0x00000006CC	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR1 reads
PCIeBar2AXIBar_2_Rd_Cache_PF2_VF	0x00000006D0	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR2 reads
PCIeBar2AXIBar_3_Rd_Cache_PF2_VF	0x00000006D4	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR3 reads
PCIeBar2AXIBar_4_Rd_Cache_PF2_VF	0x00000006D8	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR4 reads
PCIeBar2AXIBar_5_Rd_Cache_PF2_VF	0x00000006DC	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR5 reads
PCIeBar2AXIBar_6_Rd_Cache_PF2_VF	0x00000006E0	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR6 reads
PCIeBar2AXIBar_0_Wr_Sec_PF2_VF	0x00000006E4	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR0 writes
PCIeBar2AXIBar_1_Wr_Sec_PF2_VF	0x00000006E8	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR1 writes
PCIeBar2AXIBar_2_Wr_Sec_PF2_VF	0x00000006EC	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR2 writes
PCIeBar2AXIBar_3_Wr_Sec_PF2_VF	0x00000006F0	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR3 writes
PCIeBar2AXIBar_4_Wr_Sec_PF2_VF	0x00000006F4	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR4 writes
PCIeBar2AXIBar_5_Wr_Sec_PF2_VF	0x00000006F8	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR5 writes
PCIeBar2AXIBar_6_Wr_Sec_PF2_VF	0x00000006FC	32	rwNormal read/write	0x00000000	ARPROT value for PF2 VF BAR6 writes
PCIeBar2AXIBar_0_Wr_Cache_PF2_VF	0x0000000700	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR0 writes
PCIeBar2AXIBar_1_Wr_Cache_PF2_VF	0x0000000704	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR1 writes
PCIeBar2AXIBar_2_Wr_Cache_PF2_VF	0x0000000708	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR2 writes
PCIeBar2AXIBar_3_Wr_Cache_PF2_VF	0x000000070C	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR3 writes
PCIeBar2AXIBar_4_Wr_Cache_PF2_VF	0x0000000710	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR4 writes
PCIeBar2AXIBar_5_Wr_Cache_PF2_VF	0x0000000714	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR5 writes
PCIeBar2AXIBar_6_Wr_Cache_PF2_VF	0x0000000718	32	rwNormal read/write	0x00000000	ARCACHE value for PF2 VF BAR6 writes
PCIeBar2AXIBar_0_Len_PF2_VF	0x000000071C	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 VF BAR0
PCIeBar2AXIBar_1_Len_PF2_VF	0x0000000720	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 VF BAR1
PCIeBar2AXIBar_2_Len_PF2_VF	0x0000000724	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 VF BAR2
PCIeBar2AXIBar_3_Len_PF2_VF	0x0000000728	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 VF BAR3
PCIeBar2AXIBar_4_Len_PF2_VF	0x000000072C	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 VF BAR4
PCIeBar2AXIBar_5_Len_PF2_VF	0x0000000730	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 VF BAR5
PCIeBar2AXIBar_6_Len_PF2_VF	0x0000000734	32	rwNormal read/write	0x00000000	Bar size in bits for PF2 VF BAR6
PCIeBar2AXIBar_0_bar_PF3_VF_L	0x0000000738	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR0
PCIeBar2AXIBar_0_bar_PF3_VF_H	0x000000073C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR0
PCIeBar2AXIBar_1_bar_PF3_VF_L	0x0000000740	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR1
PCIeBar2AXIBar_1_bar_PF3_VF_H	0x0000000744	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR1
PCIeBar2AXIBar_2_bar_PF3_VF_L	0x0000000748	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR2
PCIeBar2AXIBar_2_bar_PF3_VF_H	0x000000074C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR2
PCIeBar2AXIBar_3_bar_PF3_VF_L	0x0000000750	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR3
PCIeBar2AXIBar_3_bar_PF3_VF_H	0x0000000754	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR3
PCIeBar2AXIBar_4_bar_PF3_VF_L	0x0000000758	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VFBAR4
PCIeBar2AXIBar_4_bar_PF3_VF_H	0x000000075C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VFBAR4
PCIeBar2AXIBar_5_bar_PF3_VF_L	0x0000000760	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR5
PCIeBar2AXIBar_5_bar_PF3_VF_H	0x0000000764	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR5
PCIeBar2AXIBar_6_bar_PF3_VF_L	0x0000000768	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR6
PCIeBar2AXIBar_6_bar_PF3_VF_H	0x000000076C	32	rwNormal read/write	0x00000000	Bits[63:12] Bar Translation for PF3 VF BAR6
PCIeBar2AXIBar_0_Rd_Sec_PF3_VF	0x0000000770	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR0 reads
PCIeBar2AXIBar_1_Rd_Sec_PF3_VF	0x0000000774	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR1 reads
PCIeBar2AXIBar_2_Rd_Sec_PF3_VF	0x0000000778	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR2 reads
PCIeBar2AXIBar_3_Rd_Sec_PF3_VF	0x000000077C	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR3 reads
PCIeBar2AXIBar_4_Rd_Sec_PF3_VF	0x0000000780	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR4 reads
PCIeBar2AXIBar_5_Rd_Sec_PF3_VF	0x0000000784	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR5 reads
PCIeBar2AXIBar_6_Rd_Sec_PF3_VF	0x0000000788	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR6 reads
PCIeBar2AXIBar_0_Rd_Cache_PF3_VF	0x000000078C	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR0 reads
PCIeBar2AXIBar_1_Rd_Cache_PF3_VF	0x0000000790	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR1 reads
PCIeBar2AXIBar_2_Rd_Cache_PF3_VF	0x0000000794	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR2 reads
PCIeBar2AXIBar_3_Rd_Cache_PF3_VF	0x0000000798	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR3 reads
PCIeBar2AXIBar_4_Rd_Cache_PF3_VF	0x000000079C	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR4 reads
PCIeBar2AXIBar_5_Rd_Cache_PF3_VF	0x00000007A0	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR5 reads
PCIeBar2AXIBar_6_Rd_Cache_PF3_VF	0x00000007A4	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR6 reads
PCIeBar2AXIBar_0_Wr_Sec_PF3_VF	0x00000007A8	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR0 writes
PCIeBar2AXIBar_1_Wr_Sec_PF3_VF	0x00000007AC	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR1 writes
PCIeBar2AXIBar_2_Wr_Sec_PF3_VF	0x00000007B0	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR2 writes
PCIeBar2AXIBar_3_Wr_Sec_PF3_VF	0x00000007B4	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR3 writes
PCIeBar2AXIBar_4_Wr_Sec_PF3_VF	0x00000007B8	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR4 writes
PCIeBar2AXIBar_5_Wr_Sec_PF3_VF	0x00000007BC	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR5 writes
PCIeBar2AXIBar_6_Wr_Sec_PF3_VF	0x00000007C0	32	rwNormal read/write	0x00000000	ARPROT value for PF3 VF BAR6 writes
PCIeBar2AXIBar_0_Wr_Cache_PF3_VF	0x00000007C4	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR0 writes
PCIeBar2AXIBar_1_Wr_Cache_PF3_VF	0x00000007C8	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR1 writes
PCIeBar2AXIBar_2_Wr_Cache_PF3_VF	0x00000007CC	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR2 writes
PCIeBar2AXIBar_3_Wr_Cache_PF3_VF	0x00000007D0	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR3 writes
PCIeBar2AXIBar_4_Wr_Cache_PF3_VF	0x00000007D4	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR4 writes
PCIeBar2AXIBar_5_Wr_Cache_PF3_VF	0x00000007D8	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR5 writes
PCIeBar2AXIBar_6_Wr_Cache_PF3_VF	0x00000007DC	32	rwNormal read/write	0x00000000	ARCACHE value for PF3 VF BAR6 writes
PCIeBar2AXIBar_0_Len_PF3_VF	0x00000007E0	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 VF BAR0
PCIeBar2AXIBar_1_Len_PF3_VF	0x00000007E4	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 VF BAR1
PCIeBar2AXIBar_2_Len_PF3_VF	0x00000007E8	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 VF BAR2
PCIeBar2AXIBar_3_Len_PF3_VF	0x00000007EC	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 VF BAR3
PCIeBar2AXIBar_4_Len_PF3_VF	0x00000007F0	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 VF BAR4
PCIeBar2AXIBar_5_Len_PF3_VF	0x00000007F4	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 VF BAR5
PCIeBar2AXIBar_6_Len_PF3_VF	0x00000007F8	32	rwNormal read/write	0x00000000	Bar size in bits for PF3 VF BAR6
PF0_Rd_Sec	0x00000007FC	32	rwNormal read/write	0x00000000	multiq AXIMM ARPROT setting
PF1_Rd_Sec	0x0000000800	32	rwNormal read/write	0x00000000	multiq AXIMM ARPROT setting
PF2_Rd_Sec	0x0000000804	32	rwNormal read/write	0x00000000	multiq AXIMM ARPROT setting
PF3_Rd_Sec	0x0000000808	32	rwNormal read/write	0x00000000	multiq AXIMM ARPROT setting
PF0_Wr_Sec	0x000000080C	32	rwNormal read/write	0x00000000	multiq AIXMM_AWPROT setting
PF1_Wr_Sec	0x0000000810	32	rwNormal read/write	0x00000000	multiq AIXMM_AWPROT setting
PF2_Wr_Sec	0x0000000814	32	rwNormal read/write	0x00000000	multiq AIXMM_AWPROT setting
PF3_Wr_Sec	0x0000000818	32	rwNormal read/write	0x00000000	multiq AIXMM_AWPROT setting
PF0_VF_Rd_Sec	0x000000081C	32	rwNormal read/write	0x00000000	multiq MM ARPROT setting
PF1_VF_Rd_Sec	0x0000000820	32	rwNormal read/write	0x00000000	multiq MM ARPROT setting
PF2_VF_Rd_Sec	0x0000000824	32	rwNormal read/write	0x00000000	multiq MM ARPROT setting
PF3_VF_Rd_Sec	0x0000000828	32	rwNormal read/write	0x00000000	multiq MM ARPROT setting
PF0_VF_Wr_Sec	0x000000082C	32	rwNormal read/write	0x00000000	multiq AIXMM_AWPROT setting
PF1_VF_Wr_Sec	0x0000000830	32	rwNormal read/write	0x00000000	multiq AIXMM_AWPROT setting
PF2_VF_Wr_Sec	0x0000000834	32	rwNormal read/write	0x00000000	multiq AIXMM_AWPROT setting
PF3_VF_Wr_Sec	0x0000000838	32	rwNormal read/write	0x00000000	multiq AIXMM_AWPROT setting
PF0_Rd_Cache	0x000000083C	32	rwNormal read/write	0x00000000	multiq AXIMM ARCACHE setting
PF1_Rd_Cache	0x0000000840	32	rwNormal read/write	0x00000000	multiq AXIMM ARCACHE setting
PF2_Rd_Cache	0x0000000844	32	rwNormal read/write	0x00000000	multiq AXIMM ARCACHE setting
PF3_Rd_Cache	0x0000000848	32	rwNormal read/write	0x00000000	multiq AXIMM ARCACHE setting
PF0_Wr_Cache	0x000000084C	32	rwNormal read/write	0x00000000	multiq AIXMM_AWCACHE setting
PF1_Wr_Cache	0x0000000850	32	rwNormal read/write	0x00000000	multiq AIXMM_AWCACHE setting
PF2_Wr_Cache	0x0000000854	32	rwNormal read/write	0x00000000	multiq AIXMM_AWCACHE setting
PF3_Wr_Cache	0x0000000858	32	rwNormal read/write	0x00000000	multiq AIXMM_AWCACHE setting
PF0_VF_Rd_Cache	0x000000085C	32	rwNormal read/write	0x00000000	multiq MM ARCACHE setting
PF1_VF_Rd_Cache	0x0000000860	32	rwNormal read/write	0x00000000	multiq MM ARCACHE setting
PF2_VF_Rd_Cache	0x0000000864	32	rwNormal read/write	0x00000000	multiq MM ARCACHE setting
PF3_VF_Rd_Cache	0x0000000868	32	rwNormal read/write	0x00000000	multiq MM ARCACHE setting
PF0_VF_Wr_Cache	0x000000086C	32	rwNormal read/write	0x00000000	multiq AIXMM_AWCACHE setting
PF1_VF_Wr_Cache	0x0000000870	32	rwNormal read/write	0x00000000	multiq AIXMM_AWCACHE setting
PF2_VF_Wr_Cache	0x0000000874	32	rwNormal read/write	0x00000000	multiq AIXMM_AWCACHE setting
PF3_VF_Wr_Cache	0x0000000878	32	rwNormal read/write	0x00000000	multiq AIXMM_AWCACHE setting
PF0_Num_VFs	0x000000087C	32	rwNormal read/write	0x00000000	number of VFs assigned to a PF, when 0, the 1stvf_offset is invalid
PF1_Num_VFs	0x0000000880	32	rwNormal read/write	0x00000000	number of VFs assigned to a PF, when 0, the 1stvf_offset is invalid
PF2_Num_VFs	0x0000000884	32	rwNormal read/write	0x00000000	number of VFs assigned to a PF, when 0, the 1stvf_offset is invalid
PF3_Num_VFs	0x0000000888	32	rwNormal read/write	0x00000000	number of VFs assigned to a PF, when 0, the 1stvf_offset is invalid
PF0_1stvf_Offset	0x000000088C	32	rwNormal read/write	0x00000000	the function offset to the 1st VF within the PF
PF1_1stvf_Offset	0x0000000890	32	rwNormal read/write	0x00000000	the function offset to the 1st VF within the PF
PF2_1stvf_Offset	0x0000000894	32	rwNormal read/write	0x00000000	the function offset to the 1st VF within the PF
PF3_1stvf_Offset	0x0000000898	32	rwNormal read/write	0x00000000	the function offset to the 1st VF within the PF
Ch0_En	0x000000089C	32	rwNormal read/write	0x00000000	channel enable. Must be contiguous
Ch0_Rd_Sec	0x00000008A0	32	rwNormal read/write	0x00000000	ARPROT value used for DMA AXIMM reads from channel0
Ch0_Wr_Sec	0x00000008A4	32	rwNormal read/write	0x00000000	ARPROT value used for DMA AXIMM writes from channel0
Ch0_Rd_Cache	0x00000008A8	32	rwNormal read/write	0x00000000	ARCACHE value used for DMA AXIMM reads from channel0
Ch0_Wr_Cache	0x00000008AC	32	rwNormal read/write	0x00000000	ARCACHE value used for DMA AXIMM writes from channel0
Ch0_c2h_AXI_dsc	0x00000008B0	32	rwNormal read/write	0x00000000	Fetch descriptors from AXI MM interface
Ch0_H2c_AXI_dsc	0x00000008B4	32	rwNormal read/write	0x00000000	Fetch descriptors from AXI MM interface
Ch0_PFid	0x00000008B8	32	rwNormal read/write	0x00000000	The PF to which the channel is assigned
Ch0_MultQ	0x00000008BC	32	rwNormal read/write	0x00000000	The channel has multiq enabled. 1 - MULTQ, 0 - XDMA
Ch0_Stream	0x00000008C0	32	rwNormal read/write	0x00000000	The channel is streaming vs memory mapped.
Ch0_MM_Port	0x00000008C4	32	rwNormal read/write	0x00000000	The routing hint bit inserted into address[50] to determine which MM port transactions from this channel are mastered on. Requires that the axi_mm_dma_steering mode is set to mapped.
Ch1_En	0x00000008C8	32	rwNormal read/write	0x00000000	channel enable. Must be contiguous
Ch1_Rd_Sec	0x00000008CC	32	rwNormal read/write	0x00000000	ARPROT value used for DMA AXIMM reads from channel1
Ch1_Wr_Sec	0x00000008D0	32	rwNormal read/write	0x00000000	ARPROT value used for DMA AXIMM writes from channel1
Ch1_Rd_Cache	0x00000008D4	32	rwNormal read/write	0x00000000	ARCACHE value used for DMA AXIMM reads from channel1
Ch1_Wr_Cache	0x00000008D8	32	rwNormal read/write	0x00000000	ARCACHE value used for DMA AXIMM writes from channel1
Ch1_c2h_AXI_dsc	0x00000008DC	32	rwNormal read/write	0x00000000	Fetch descriptors from AXI MM interface
Ch1_H2c_AXI_dsc	0x00000008E0	32	rwNormal read/write	0x00000000	Fetch descriptors from AXI MM interface
Ch1_PFid	0x00000008E4	32	rwNormal read/write	0x00000000	The PF to which the channel is assigned
Ch1_MultQ	0x00000008E8	32	rwNormal read/write	0x00000000	The channel has multiq enabled. 1 - MULTQ, 0 - XDMA
Ch1_Stream	0x00000008EC	32	rwNormal read/write	0x00000000	The channel is streaming vs memory mapped.
Ch1_MM_Port	0x00000008F0	32	rwNormal read/write	0x00000000	The routing hint bit inserted into address[50] to determine which MM port transactions from this channel are mastered on. Requires that the axi_mm_dma_steering mode is set to mapped.
Ch2_En	0x00000008F4	32	rwNormal read/write	0x00000000	channel enable. Must be contiguous
Ch2_Rd_Sec	0x00000008F8	32	rwNormal read/write	0x00000000	ARPROT value used for DMA AXIMM reads from channel2
Ch2_Wr_Sec	0x00000008FC	32	rwNormal read/write	0x00000000	ARPROT value used for DMA AXIMM writes from channel2
Ch2_Rd_Cache	0x0000000900	32	rwNormal read/write	0x00000000	ARCACHE value used for DMA AXIMM reads from channel2
Ch2_Wr_Cache	0x0000000904	32	rwNormal read/write	0x00000000	ARCACHE value used for DMA AXIMM writes from channel2
Ch2_c2h_AXI_dsc	0x0000000908	32	rwNormal read/write	0x00000000	Fetch descriptors from AXI MM interface
Ch2_H2c_AXI_dsc	0x000000090C	32	rwNormal read/write	0x00000000	Fetch descriptors from AXI MM interface
Ch2_PFid	0x0000000910	32	rwNormal read/write	0x00000000	The PF to which the channel is assigned
Ch2_MultQ	0x0000000914	32	rwNormal read/write	0x00000000	The channel has multiq enabled. 1 - MULTQ, 0 - XDMA
Ch2_Stream	0x0000000918	32	rwNormal read/write	0x00000000	The channel is streaming vs memory mapped.
Ch2_MM_Port	0x000000091C	32	rwNormal read/write	0x00000000	The routing hint bit inserted into address[50] to determine which MM port transactions from this channel are mastered on. Requires that the axi_mm_dma_steering mode is set to mapped.
Ch3_En	0x0000000920	32	rwNormal read/write	0x00000000	channel enable. Must be contiguous
Ch3_Rd_Sec	0x0000000924	32	rwNormal read/write	0x00000000	ARPROT value used for DMA AXIMM reads from channel3
Ch3_Wr_Sec	0x0000000928	32	rwNormal read/write	0x00000000	ARPROT value used for DMA AXIMM writes from channel3
Ch3_Rd_Cache	0x000000092C	32	rwNormal read/write	0x00000000	ARCACHE value used for DMA AXIMM reads from channel3
Ch3_Wr_Cache	0x0000000930	32	rwNormal read/write	0x00000000	ARCACHE value used for DMA AXIMM writes from channel3
Ch3_c2h_AXI_dsc	0x0000000934	32	rwNormal read/write	0x00000000	Fetch descriptors from AXI MM interface
Ch3_h2c_AXI_dsc	0x0000000938	32	rwNormal read/write	0x00000000	Fetch descriptors from AXI MM interface
Ch3_PFid	0x000000093C	32	rwNormal read/write	0x00000000	The PF to which the channel is assigned
Ch3_MultQ	0x0000000940	32	rwNormal read/write	0x00000000	The channel has multiq enabled. 1 - MULTQ, 0 - XDMA
Ch3_Stream	0x0000000944	32	rwNormal read/write	0x00000000	The channel is streaming vs memory mapped.
Ch3_MM_Port	0x0000000948	32	rwNormal read/write	0x00000000	The routing hint bit inserted into address[50] to determine which MM port transactions from this channel are mastered on. Requires that the axi_mm_dma_steering mode is set to mapped.
pf0_Ch_Alloc	0x000000094C	32	rwNormal read/write	0x00000000	1 Hot indicating which channels are allocated to this PF. Channel allocation must be packed and start with 0. Lower PF must be allocated lower channel bits. Channels allocated among different PFs must not overlap.
pf1_Ch_Alloc	0x0000000950	32	rwNormal read/write	0x00000000	1 Hot indicating which channels are allocated to this PF. Channel allocation must be packed and start with 0. Lower PF must be allocated lower channel bits. Channels allocated among different PFs must not overlap.
pf2_Ch_Alloc	0x0000000954	32	rwNormal read/write	0x00000000	1 Hot indicating which channels are allocated to this PF. Channel allocation must be packed and start with 0. Lower PF must be allocated lower channel bits. Channels allocated among different PFs must not overlap.
pf3_Ch_Alloc	0x0000000958	32	rwNormal read/write	0x00000000	1 Hot indicating which channels are allocated to this PF. Channel allocation must be packed and start with 0. Lower PF must be allocated lower channel bits. Channels allocated among different PFs must not overlap.
Design_Use_Mode	0x0000000E00	32	rwNormal read/write	0x00000000	Indicates Architectural Modes of operation of PCIe-A core
Enable_Port1	0x0000000E04	1	rwNormal read/write	0x00000000	Enable Port #1. When DESIGN_USE_MODE is 0000100b (Port #0 DMA Mode), used to Enable Port #1 operation in the Streaming Mode
cpm_pciea_dma_dbg	0x0000000E08	32	rwNormal read/write	0x00000000	cpm_pciea_dma_dbg