Cfg_CRS_Sw_Visible_En (CPM4_DMA_ATTR) Register Description
| Register Name | Cfg_CRS_Sw_Visible_En |
|---|---|
| Relative Address | 0x00000000A8 |
| Absolute Address | 0x00FCA700A8 (CPM4_DMA_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | CRS error response disable for CfgRd requests. In case of PCIE core returns a CRS response on RC interface: If attr_dma_cfg_crs_sw_visible_en=1, it returns OK on axilite response and 0xFFFF0001 on data bus. If 0, the request is sent to PCIE again (upto 256 times) to look for a successful response. If a 'CRS' response is still returned by the PCIE core, a 'DECERR' response is returned on the rresp bus. |
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_cfg_crs_sw_visible_en
Cfg_CRS_Sw_Visible_En (CPM4_DMA_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 | CRS error response disable for CfgRd requests. In case of PCIE core returns a CRS response on RC interface: If attr_dma_cfg_crs_sw_visible_en=1, it returns OK on axilite response and 0xFFFF0001 on data bus. If 0, the request is sent to PCIE again (upto 256 times) to look for a successful response. If a 'CRS' response is still returned by the PCIE core, a 'DECERR' response is returned on the rresp bus. |