Ch1_MM_Port (CPM4_DMA_ATTR) Register Description
| Register Name | Ch1_MM_Port |
|---|---|
| Relative Address | 0x00000008F0 |
| Absolute Address | 0x00FCA708F0 (CPM4_DMA_ATTR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | The routing hint bit inserted into address[50] to determine which MM port transactions from this channel are mastered on. Requires that the axi_mm_dma_steering mode is set to mapped. |
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_ch1_mm_port
Ch1_MM_Port (CPM4_DMA_ATTR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr | 0 | rwNormal read/write | 0x0 | The routing hint bit inserted into address[50] to determine which MM port transactions from this channel are mastered on. Requires that the axi_mm_dma_steering mode is set to mapped. |