Ch1_Wr_Cache (CPM4_DMA_ATTR) Register Description
Register Name | Ch1_Wr_Cache |
Relative Address | 0x00000008D8 |
Absolute Address |
0x00FCA708D8 (CPM4_DMA_ATTR)
|
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | ARCACHE value used for DMA AXIMM writes from channel1 |
This register should only be written to during reset of the PCIe block Alternate register name: attr_dma_ch1_wr_cache
Ch1_Wr_Cache (CPM4_DMA_ATTR) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
attr | 3:0 | rwNormal read/write | 0x0 | ARCACHE value used for DMA AXIMM writes from channel1 |